Lumicity
Direct message the job poster from Lumicity
Team Leader at Lumicity - Part of the G2V Group
Located on-site in San Jose, CA Overview
This is an exciting opportunity to work on high-speed digital integrated circuits for a startup that has groundbreaking technology and has raised over $100 million in funding. You will be working on RTL Design and Coding, Clock Domain Crossing, Synthesis and Timing Closure for the company’s next generation products. Responsibilities
Contribute to RTL Design and Coding, Clock Domain Crossing, Synthesis and Timing Closure for next generation products. Collaborate with hardware and software teams to ensure design integrity across the ASIC flow. Qualifications
B.S. or M.S. in Electrical Engineering, Computer Engineering or similar Experience with Hardware Description Languages such as Verilog or SystemVerilog Strong background in Digital ASIC Design with understanding of the complete ASIC design flow from specification to tape-out Experience with Cadence or Synopsys EDA tools such as Tempus, PrimeTime, Genus, Design Compiler, Formality or JasperGold Scripting experience with Python, TCL or Perl Experience in Static Timing Analysis, Synopsys Timing Constraints, Clock Domain/Reset Domain Preferred Skills (Not Essential)
Working with protocols for Optical Communications Digital Data Communication techniques including scrambling or forward error correction (FEC) Company Benefits
401K Bonus Stock/Equity Full Premium Healthcare Seniority level
Mid-Senior level Employment type
Full-time Industries
Semiconductor Manufacturing
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Located on-site in San Jose, CA Overview
This is an exciting opportunity to work on high-speed digital integrated circuits for a startup that has groundbreaking technology and has raised over $100 million in funding. You will be working on RTL Design and Coding, Clock Domain Crossing, Synthesis and Timing Closure for the company’s next generation products. Responsibilities
Contribute to RTL Design and Coding, Clock Domain Crossing, Synthesis and Timing Closure for next generation products. Collaborate with hardware and software teams to ensure design integrity across the ASIC flow. Qualifications
B.S. or M.S. in Electrical Engineering, Computer Engineering or similar Experience with Hardware Description Languages such as Verilog or SystemVerilog Strong background in Digital ASIC Design with understanding of the complete ASIC design flow from specification to tape-out Experience with Cadence or Synopsys EDA tools such as Tempus, PrimeTime, Genus, Design Compiler, Formality or JasperGold Scripting experience with Python, TCL or Perl Experience in Static Timing Analysis, Synopsys Timing Constraints, Clock Domain/Reset Domain Preferred Skills (Not Essential)
Working with protocols for Optical Communications Digital Data Communication techniques including scrambling or forward error correction (FEC) Company Benefits
401K Bonus Stock/Equity Full Premium Healthcare Seniority level
Mid-Senior level Employment type
Full-time Industries
Semiconductor Manufacturing
#J-18808-Ljbffr