Fidelis Companies
Digital Signal Processing (DSP) Engineer
Fidelis Companies, San Jose, California, United States, 95199
Overview
A pioneering force in semiconductor innovation is expanding its Optical Systems Division in San Jose. This team is at the forefront of developing ultra-high-speed connectivity solutions for modern data centers, blending deep technical expertise with a culture of collaboration and excellence. About the Company
(existing description consolidated above) Role Overview
We’re looking for a seasoned engineer with a strong background in digital signal processing to contribute to the design of advanced SerDes architectures. This role involves crafting high-performance DSP blocks that enable next-generation optical and electrical interconnects, with a focus on scalability, efficiency, and integration. Key Responsibilities
Architect and implement DSP logic for high-speed serial communication systems Convert complex PAM4-based equalization and clock recovery algorithms into synthesizable Verilog Collaborate across design, verification, and system teams to ensure seamless integration Conduct timing analysis, synthesis, and simulation using industry-standard tools Develop RTL that aligns with DFT methodologies and supports robust testing Analyze parasitic effects and validate performance through annotated simulations Apply best practices in signal and power integrity modeling for high-speed designs Qualifications
Advanced degree (MS or PhD) in Electrical or Computer Engineering Minimum of 8 years in DSP-focused SerDes development for data center applications Strong command of Verilog/SystemVerilog and simulation environments Deep familiarity with PAM4 signaling and associated design trade-offs Experience with adaptation algorithms (FFE, DFE, CDR) and high-speed ADCs Exposure to mixed-signal modeling and AMS simulation techniques Proven ability to optimize logic for power, timing, and testability Excellent communication skills and a collaborative mindset
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A pioneering force in semiconductor innovation is expanding its Optical Systems Division in San Jose. This team is at the forefront of developing ultra-high-speed connectivity solutions for modern data centers, blending deep technical expertise with a culture of collaboration and excellence. About the Company
(existing description consolidated above) Role Overview
We’re looking for a seasoned engineer with a strong background in digital signal processing to contribute to the design of advanced SerDes architectures. This role involves crafting high-performance DSP blocks that enable next-generation optical and electrical interconnects, with a focus on scalability, efficiency, and integration. Key Responsibilities
Architect and implement DSP logic for high-speed serial communication systems Convert complex PAM4-based equalization and clock recovery algorithms into synthesizable Verilog Collaborate across design, verification, and system teams to ensure seamless integration Conduct timing analysis, synthesis, and simulation using industry-standard tools Develop RTL that aligns with DFT methodologies and supports robust testing Analyze parasitic effects and validate performance through annotated simulations Apply best practices in signal and power integrity modeling for high-speed designs Qualifications
Advanced degree (MS or PhD) in Electrical or Computer Engineering Minimum of 8 years in DSP-focused SerDes development for data center applications Strong command of Verilog/SystemVerilog and simulation environments Deep familiarity with PAM4 signaling and associated design trade-offs Experience with adaptation algorithms (FFE, DFE, CDR) and high-speed ADCs Exposure to mixed-signal modeling and AMS simulation techniques Proven ability to optimize logic for power, timing, and testability Excellent communication skills and a collaborative mindset
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