Mogi I/O : OTT/Podcast/Short Video Apps for you
Senior AMS Design & Verification Engineer (Austin, TX)
Mogi I/O : OTT/Podcast/Short Video Apps for you, Dallas, Texas, United States, 75215
Senior Mixed-Signal Verification Engineer – Semiconductor (Austin, TX)
Work type: Full-time, Onsite (Austin, Texas). Experience required: 5+ years. Employment type: Direct hire (core team, well-funded startup). Sponsorship: Likely H1B/EAD eligible.
Our client is a Series-D semiconductor innovator, specializing in programmable coherent DSP solutions that power cloud and AI infrastructure. Their breakthrough DSP technology underpins high-speed data-center interconnects, enabling faster, more efficient cloud and AI communications. Backed by $180 million in investment from Kleiner Perkins, Spark Capital, Mayfield, and Fidelity, the company is out of stealth and scaling rapidly to support the future of AI-driven connectivity.
Job overview: The role focuses on mixed-signal verification for advanced DSP-based communication and AI interconnect chips. You’ll develop behavioral models for analog blocks, run mixed-signal dynamic verification, and collaborate with world-class analog and digital design teams to validate next-generation coherent DSP solutions.
Key Responsibilities
Perform behavioral modeling (BM) of analog designs to enable digital verification.
Conduct mixed-signal dynamic verification (without AMS) using chip-level digital design tools.
Write, simulate, and debug Verilog/SystemVerilog code for verification.
Use Cadence Virtuoso schematics to interface with analog designs.
Develop test plans, verification strategies, and scalable testbench automation.
Collaborate with DSP, analog, and digital engineering teams to validate high-speed designs.
Present verification results, maintain coverage metrics, and ensure first-pass success in silicon.
Minimum Qualifications
5+ years of mixed-signal verification experience.
Strong background in behavioral modeling for analog-to-digital verification.
Hands-on Verilog/SystemVerilog verification coding.
Familiarity with Virtuoso schematics.
Basic understanding of analog design fundamentals.
Preferred Qualifications
Experience with UVM (Universal Verification Methodology).
Background working with both Synopsys and Cadence verification tools.
Understanding of advanced verification infrastructure – simulators, waveform viewers, coverage, execution automation.
Proven track record of building portable/scalable test environments.
Strong communication skills; ability to write test plans, document results, and present to multidisciplinary teams.
Location: Austin, Texas. (Onsite)
#J-18808-Ljbffr
Our client is a Series-D semiconductor innovator, specializing in programmable coherent DSP solutions that power cloud and AI infrastructure. Their breakthrough DSP technology underpins high-speed data-center interconnects, enabling faster, more efficient cloud and AI communications. Backed by $180 million in investment from Kleiner Perkins, Spark Capital, Mayfield, and Fidelity, the company is out of stealth and scaling rapidly to support the future of AI-driven connectivity.
Job overview: The role focuses on mixed-signal verification for advanced DSP-based communication and AI interconnect chips. You’ll develop behavioral models for analog blocks, run mixed-signal dynamic verification, and collaborate with world-class analog and digital design teams to validate next-generation coherent DSP solutions.
Key Responsibilities
Perform behavioral modeling (BM) of analog designs to enable digital verification.
Conduct mixed-signal dynamic verification (without AMS) using chip-level digital design tools.
Write, simulate, and debug Verilog/SystemVerilog code for verification.
Use Cadence Virtuoso schematics to interface with analog designs.
Develop test plans, verification strategies, and scalable testbench automation.
Collaborate with DSP, analog, and digital engineering teams to validate high-speed designs.
Present verification results, maintain coverage metrics, and ensure first-pass success in silicon.
Minimum Qualifications
5+ years of mixed-signal verification experience.
Strong background in behavioral modeling for analog-to-digital verification.
Hands-on Verilog/SystemVerilog verification coding.
Familiarity with Virtuoso schematics.
Basic understanding of analog design fundamentals.
Preferred Qualifications
Experience with UVM (Universal Verification Methodology).
Background working with both Synopsys and Cadence verification tools.
Understanding of advanced verification infrastructure – simulators, waveform viewers, coverage, execution automation.
Proven track record of building portable/scalable test environments.
Strong communication skills; ability to write test plans, document results, and present to multidisciplinary teams.
Location: Austin, Texas. (Onsite)
#J-18808-Ljbffr