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Quinnel Soft LLC

Lead AI Engineer – LLM Systems for Hardware Design

Quinnel Soft LLC, Trenton, New Jersey, United States

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Lead AI Engineer – LLM Systems for Hardware Design Direct message the job poster from Quinnel Soft LLC

We’re building next-generation AI systems that help hardware engineers

write, verify, and optimize Verilog and RTL code

using large language models (LLMs).

As a

Lead AI Engineer , you’ll guide the design and deployment of specialized LLMs that make chip design smarter, faster, and more secure. You’ll lead a high-impact team that combines advanced AI modeling with enterprise‑grade privacy and compliance principles.

What You’ll Do

Architect and lead LLM development

for hardware and EDA workflows—from fine‑tuning and evaluation to production rollout.

Design secure ML infrastructure

on AWS using Bedrock, SageMaker, and EKS, ensuring data protection, encryption, and compliance.

Experiment with advanced fine‑tuning techniques

(LoRA/QLoRA, PEFT, RLAIF) to adapt foundation models for HDL code generation and analysis.

Establish performance benchmarks

using compile, simulate, and synthesis‑based metrics to measure functional accuracy and reliability.

Integrate AI tools

into developer environments (IDEs, CI pipelines, and internal retrieval systems).

Mentor engineers

in ML best practices, reproducibility, and privacy‑first development.

Collaborate across teams —working closely with hardware, EDA, and security experts to manage data, compliance, and delivery.

What You’ll Bring

10+ years in software or ML engineering, including 5+ in applied ML and 3+ with LLM or transformer‑based systems.

Expertise with

PyTorch, Hugging Face Transformers, PEFT, TRL, DeepSpeed, FSDP , and large‑scale training.

Proven experience building on

AWS ML infrastructure —Bedrock, SageMaker, EKS, S3, IAM, KMS, PrivateLink, CloudTrail.

Solid programming experience in

Python

with strong CI/CD and MLOps practices.

Strong leadership, problem‑solving, and communication skills to align multi‑disciplinary teams.

Nice to Have

Background in

Verilog, SystemVerilog, or RTL

design and EDA workflows (linting, synthesis, simulation).

Knowledge of

grammar‑constrained decoding ,

RAG , or

AST‑aware code modeling .

Familiarity with

vLLM, TensorRT‑LLM , or other inference optimization frameworks.

Experience with

AI governance, DLP, or data anonymization

for enterprise environments.

What Success Looks Like

90 Days:

Secure and compliant AWS LLM training environment established; baseline model deployed.

6 Months:

Multi‑model fine‑tuning and retrieval integration for spec‑to‑RTL translation.

12 Months:

Demonstrated productivity gains—faster code validation, improved lint outcomes, and measurable design acceleration.

Modeling:

PyTorch, Transformers, DeepSpeed, TensorRT‑LLM, vLLM

Security:

S3 + KMS, IAM, PrivateLink, CloudTrail, Step Functions

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