Microsoft Corporation
Senior Implementation Engineer
Microsoft Corporation, Redmond, Washington, United States, 98052
Microsoft
Silicon, Cloud Hardware, and Infrastructure Engineering
(SCHIE)
is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
The
Compute Silicon & Manufacturing Engineering
(CSME)
organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the
CSME
team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a
Senior Implementation Engineer
to join the team.
Responsibilities
You will be a key link between front-end design and back-end teams. As a leader in the enablement of quality RTL and collateral file drops to PD, you will be responsible for implementing feedback and mitigations in the design constraints and toolchain to ensure best-case PPA. Strong communication skills will be needed to coordinate with RTL, DFT, CAD and physical design teams.
You will participate in flow development, design automation, and correlation exercises to back-end flows. You are expected to work with limited direction and have attention to detail. You will also be expected to be able to provide crisp status of progress, issues, and risks on the program to the management team.
Qualifications
Required Qualifications:
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
OR equivalent experience.
5+ years of experience in the industry working on logic design, timing and synthesis
Experience in design checks including LEC, Lint, CDC/RDC
Experience in static timing analysis
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:
Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
8+ years of experience in hardware design
8+ years of experience in Synthesis, Timing constraints, Front-end design checks and Power Performance Area (PPA) trade-offs
Proficiency in all of the below:
Collateral development including timing and synthesis constraints
Front-end design checks including LEC, Lint, Formal Equivalence, and CDC/RDC
Recent synthesis tool capabilities and methods for QoR improvement
Static timing analysis
DFT insertion flows and timing constraints
Translating physical design results into feedback for flow or RTL improvement
Tcl, Perl, Python, shell programming
Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification
Experience with the project-level setup and configuration of 1 or more of the tools related to above disciplines
Knowledge of full RTL2GDS flow
Experience in ICC, power integrity analysis, ESD, PV
Good communication and self-motivated that can collaborate with larger teams within Microsoft.
Occasional travel
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay
Microsoft will accept applications for the role until November 10,2025.
#SCHIE #CSME
Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .
Silicon, Cloud Hardware, and Infrastructure Engineering
(SCHIE)
is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
The
Compute Silicon & Manufacturing Engineering
(CSME)
organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the
CSME
team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a
Senior Implementation Engineer
to join the team.
Responsibilities
You will be a key link between front-end design and back-end teams. As a leader in the enablement of quality RTL and collateral file drops to PD, you will be responsible for implementing feedback and mitigations in the design constraints and toolchain to ensure best-case PPA. Strong communication skills will be needed to coordinate with RTL, DFT, CAD and physical design teams.
You will participate in flow development, design automation, and correlation exercises to back-end flows. You are expected to work with limited direction and have attention to detail. You will also be expected to be able to provide crisp status of progress, issues, and risks on the program to the management team.
Qualifications
Required Qualifications:
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
OR equivalent experience.
5+ years of experience in the industry working on logic design, timing and synthesis
Experience in design checks including LEC, Lint, CDC/RDC
Experience in static timing analysis
Other Requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:
Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
8+ years of experience in hardware design
8+ years of experience in Synthesis, Timing constraints, Front-end design checks and Power Performance Area (PPA) trade-offs
Proficiency in all of the below:
Collateral development including timing and synthesis constraints
Front-end design checks including LEC, Lint, Formal Equivalence, and CDC/RDC
Recent synthesis tool capabilities and methods for QoR improvement
Static timing analysis
DFT insertion flows and timing constraints
Translating physical design results into feedback for flow or RTL improvement
Tcl, Perl, Python, shell programming
Familiarity with RTL and gate-level power analysis/optimization, UPF, and power-intent verification
Experience with the project-level setup and configuration of 1 or more of the tools related to above disciplines
Knowledge of full RTL2GDS flow
Experience in ICC, power integrity analysis, ESD, PV
Good communication and self-motivated that can collaborate with larger teams within Microsoft.
Occasional travel
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay
Microsoft will accept applications for the role until November 10,2025.
#SCHIE #CSME
Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .