Talently
Principal Recruiter at Talently Recruiting
Job Title:
Senior Package Engineer
Location:
On Site - San Jose, California, United States
Skills:
Package Design, 2.5D/3D Interposer Design, SI/PI Analysis, Cadence Allegro, DFM Optimization
Base Pay Range $170,000.00/yr - $190,000.00/yr
About the Technology Company / The Opportunity Are you passionate about shaping the future of advanced AI hardware? Our client, a dynamic force in the technology industry, is pioneering next-generation infrastructure to enable smarter devices, more sustainable data centers, and transformative applications across the globe. This is an opportunity to join a rapidly growing, world‑class team dedicated to pushing the boundaries of semiconductor packaging in support of cutting‑edge artificial intelligence solutions. Be a key contributor in driving innovation and building systems that will power the next decade of technological advancement.
Responsibilities
Drive end‑to‑end substrate design from concept through tape‑out, managing OSAT partnerships to optimize cost, schedule, and Design for Manufacturing (DFM).
Design advanced 2.5D and 3D interposers for high‑speed interfaces such as UCIe, HBM, and PCIe.
Own signal integrity/power integrity (SI/PI), stack‑up definition, PDN architecture, and ensure robust multi‑Gbps performance.
Collaborate closely with silicon and hardware teams to execute co‑design, including electrical modeling (Ansys Q3D, HFSS), bump pattern optimization, and parasitics/EMI analysis.
Lead DFM reviews with vendors, resolve complex design rule conflicts, and deliver manufacturable solutions on schedule.
Must‑Have Skills
BS/MS in Electrical Engineering, Materials Science, or related field.
7+ years of hands‑on experience in advanced semiconductor packaging design.
Demonstrated expertise in advanced substrate and interposer technologies, including 2.5D/3D packaging.
Proficiency with Cadence Allegro Package Designer or similar EDA tools.
Strong co‑design and communication skills across silicon, package, and system teams.
Hands‑on experience with low‑loss PCB materials for high‑speed applications.
Familiarity with SI/PI tools such as Ansys HFSS and SIwave.
Knowledge of DRC, DFM, package reliability testing, and failure analysis.
Understanding of thermal management solutions for high‑power packages.
Nice‑to‑Have Skills
Experience managing OSAT partner relationships and manufacturing schedules.
Background in high‑volume semiconductor manufacturing environments.
Direct involvement with developing packages for AI hardware or data center applications.
Exposure to package reliability improvement initiatives and advanced thermal simulation tools.
Knowledge of emerging packaging technologies and industry trends.
Seniority Level Mid‑Senior level
Employment Type Full‑time
Job Function Computer Hardware Manufacturing
Benefits
Medical insurance
Vision insurance
401(k)
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Senior Package Engineer
Location:
On Site - San Jose, California, United States
Skills:
Package Design, 2.5D/3D Interposer Design, SI/PI Analysis, Cadence Allegro, DFM Optimization
Base Pay Range $170,000.00/yr - $190,000.00/yr
About the Technology Company / The Opportunity Are you passionate about shaping the future of advanced AI hardware? Our client, a dynamic force in the technology industry, is pioneering next-generation infrastructure to enable smarter devices, more sustainable data centers, and transformative applications across the globe. This is an opportunity to join a rapidly growing, world‑class team dedicated to pushing the boundaries of semiconductor packaging in support of cutting‑edge artificial intelligence solutions. Be a key contributor in driving innovation and building systems that will power the next decade of technological advancement.
Responsibilities
Drive end‑to‑end substrate design from concept through tape‑out, managing OSAT partnerships to optimize cost, schedule, and Design for Manufacturing (DFM).
Design advanced 2.5D and 3D interposers for high‑speed interfaces such as UCIe, HBM, and PCIe.
Own signal integrity/power integrity (SI/PI), stack‑up definition, PDN architecture, and ensure robust multi‑Gbps performance.
Collaborate closely with silicon and hardware teams to execute co‑design, including electrical modeling (Ansys Q3D, HFSS), bump pattern optimization, and parasitics/EMI analysis.
Lead DFM reviews with vendors, resolve complex design rule conflicts, and deliver manufacturable solutions on schedule.
Must‑Have Skills
BS/MS in Electrical Engineering, Materials Science, or related field.
7+ years of hands‑on experience in advanced semiconductor packaging design.
Demonstrated expertise in advanced substrate and interposer technologies, including 2.5D/3D packaging.
Proficiency with Cadence Allegro Package Designer or similar EDA tools.
Strong co‑design and communication skills across silicon, package, and system teams.
Hands‑on experience with low‑loss PCB materials for high‑speed applications.
Familiarity with SI/PI tools such as Ansys HFSS and SIwave.
Knowledge of DRC, DFM, package reliability testing, and failure analysis.
Understanding of thermal management solutions for high‑power packages.
Nice‑to‑Have Skills
Experience managing OSAT partner relationships and manufacturing schedules.
Background in high‑volume semiconductor manufacturing environments.
Direct involvement with developing packages for AI hardware or data center applications.
Exposure to package reliability improvement initiatives and advanced thermal simulation tools.
Knowledge of emerging packaging technologies and industry trends.
Seniority Level Mid‑Senior level
Employment Type Full‑time
Job Function Computer Hardware Manufacturing
Benefits
Medical insurance
Vision insurance
401(k)
#J-18808-Ljbffr