Energy Jobline ZR
Senior Hardware Engineer - Micro-Architect in Burlingame
Energy Jobline ZR, Burlingame, California, United States, 94012
Company
Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world’s first supercomputer designed for the real‑time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow’s technology, today. The company was co‑founded by technologists from MIT and Carnegie Mellon, who were previously the technical co‑founders of the Bitcoin computing company 21.
Role Quadric has created an innovative general-purpose neural processing unit (GPNPU) architecture. Quadric’s co‑optimized software and hardware is targeted to run neural network inference workloads in a wide variety of edge and endpoint devices, ranging from battery operated smart‑sensor systems to high‑performance automotive or autonomous vehicle systems. Unlike other NPUs or neural network accelerators that can only accelerate a portion of a machine‑learning graph, the Quadric GPNPU executes both NN graph code and conventional C++ DSP and control code.
This is a rare opportunity to get on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the processor design cycle.
Responsibilities
Contribute to the definition of the processor architecture by understanding its applications
Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog
Own Power, Performance & Area (PPA) optimization
Contribute to timing closure through full product cycle (front end, back end, tapeout)
Independently own a major design block and improve PPA
Develop an in-depth understanding of the architecture and SW interfaces and be able to debug issues across the full SW/HW stack
Package design for customer releases and incorporate customer feedback.
Requirements
BS/MS or Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ASIC front‑end design
Proficiency in SystemC, SystemVerilog, or Verilog
Strong background in computer architecture
Knowledge of design techniques for low power digital design
Knowledge of VCS & Verilog/C Co‑Sim
Experience in data‑parallel hardware design for high‑performance computing
Experience in FPGA design is a plus
Experience in logic synthesis and performance modeling
Nice to haves
Familiarity with automotive safety (ASIL) standards
Expected Outcomes in 12 months
Independently own a major design block and improve PPA
Develop an in-depth understanding of the architecture and SW interfaces and be able to debug issues across the full SW/HW stack
Benefits
Provide competitive salaries and meaningful equity
Provide a politics‑free community for the brilliant minds who want to make an immediate impact
Provide an opportunity for you to build long‑term career relationships
Foster an environment that allows for lasting personal relationships alongside professional ones
EEO Statement Quadric is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of citizenship, marital status, or any other protected class.
#J-18808-Ljbffr
Role Quadric has created an innovative general-purpose neural processing unit (GPNPU) architecture. Quadric’s co‑optimized software and hardware is targeted to run neural network inference workloads in a wide variety of edge and endpoint devices, ranging from battery operated smart‑sensor systems to high‑performance automotive or autonomous vehicle systems. Unlike other NPUs or neural network accelerators that can only accelerate a portion of a machine‑learning graph, the Quadric GPNPU executes both NN graph code and conventional C++ DSP and control code.
This is a rare opportunity to get on the ground floor of a revolutionary new processor architecture. As a senior member of our chip design team, you will contribute to all stages of the processor design cycle.
Responsibilities
Contribute to the definition of the processor architecture by understanding its applications
Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog
Own Power, Performance & Area (PPA) optimization
Contribute to timing closure through full product cycle (front end, back end, tapeout)
Independently own a major design block and improve PPA
Develop an in-depth understanding of the architecture and SW interfaces and be able to debug issues across the full SW/HW stack
Package design for customer releases and incorporate customer feedback.
Requirements
BS/MS or Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ASIC front‑end design
Proficiency in SystemC, SystemVerilog, or Verilog
Strong background in computer architecture
Knowledge of design techniques for low power digital design
Knowledge of VCS & Verilog/C Co‑Sim
Experience in data‑parallel hardware design for high‑performance computing
Experience in FPGA design is a plus
Experience in logic synthesis and performance modeling
Nice to haves
Familiarity with automotive safety (ASIL) standards
Expected Outcomes in 12 months
Independently own a major design block and improve PPA
Develop an in-depth understanding of the architecture and SW interfaces and be able to debug issues across the full SW/HW stack
Benefits
Provide competitive salaries and meaningful equity
Provide a politics‑free community for the brilliant minds who want to make an immediate impact
Provide an opportunity for you to build long‑term career relationships
Foster an environment that allows for lasting personal relationships alongside professional ones
EEO Statement Quadric is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of citizenship, marital status, or any other protected class.
#J-18808-Ljbffr