Energy Jobline ZR
Senior Signal Integrity Engineer (NetSec) in Santa Clara
Energy Jobline ZR, Santa Clara, California, us, 95053
About the Company
Palo Alto Networks is the cybersecurity partner of choice, protecting our digital way of life. Our vision is a world where each day is safer and more secure. We are committed to innovation and shaping the future of cybersecurity.
Your Career As a contributor in the Network Security Platform Hardware development team, you will play a key role in the complete design cycle of Palo Alto Networks Firewall and SD‑WAN hardware including selecting components, modeling and simulating memory and serdes interfaces, modeling PDN networks, defining PCB routing constraints, reviewing PCB layout, developing test plans, and performing hands‑on measurements to validate critical interfaces.
Your Impact
Collaborate with ASIC, board design, PCB layout, operations supply base management, and platform software teams.
Evaluate design trade‑offs and optimize performance, risk, cost, and manufacturability.
Contribute to ASIC package design.
Model complex 3‑dimensional structures in field‑simulation software.
Simulate channel analysis for high‑speed serdes and memory interfaces.
Design and analyze high‑speed serial links (56 Gbps and beyond) and ensure compliance with internal specs and standards.
Create and verify module/package and PCB layout rules. Perform pre‑ and post‑route signal‑integrity analysis of ASIC and multi‑chip‑module designs.
Model and analyze power delivery networks for ASIC/package/module and PCB.
Create SI test plan for coverage of all serdes, memory, and external IO interfaces.
Drive creation and implementation of test infrastructure (tools, scripts, etc.) with external vendors and internal software teams.
Perform lab measurements for design validation and simulation correlations.
Drive methodology enhancements and automation to improve performance and efficiency.
Mentor junior engineers and interns.
Qualifications
Strong background in hands‑on design and validation of high‑speed PCB and ASIC package development.
Proficient in power‑integrity design and analysis using PI simulation tools such as PowerSI/DC.
Experience with high‑speed NRZ and PAM4 serdes.
Self‑motivated with demonstrated teamwork and communication skills; ability to drive outcomes with vendors and internal teams.
Out‑of‑the‑box thinking and strong desire to innovate.
Strong EM knowledge and expertise in EM simulation tools such as HFSS, PowerDC‑SI, ADS, SiSoft.
Familiar with PCB fabrication process, dielectric material, and stack‑up design.
Solid knowledge of IEEE 802.3/OIF specifications and COM simulations.
Strong lab skills and measurement experience (VNA, TDR, real‑time scope, sampling scope, BERT).
Demonstrated troubleshooting and failure‑analysis ability.
Ability to contribute to multiple projects in a dynamic, collaborative environment.
Knowledge of optical transceivers highly desired.
The Team The engineering team is core to our mission of preventing cyberattacks. We build and innovate products that solve problems none else has tackled, constantly challenging the status quo.
Why Palo Alto Networks?
Develop NPI hardware in a creative and innovative environment.
Imagine new opportunities that impact the world.
Be part of a high‑performing team of the world's best cybersecurity companies.
Flexible work arrangements support the way you work best.
Compensation Disclosure The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non‑sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $139,000 / yr and $224,500 / yr. The offered compensation may also include restricted stock units and a bonus.
Our Commitment We’re problem solvers that take risks and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together.
Accommodations We are committed to providing reasonable accommodations for all qualified individuals. If you require assistance or accommodation due to a disability or special need, please contact us at accommodations@paloaltonetworks.com.
Equal Opportunity / EEO Palo Alto Networks is an equal opportunity employer. We celebrate an inclusive workplace and provide consideration for all qualified applicants without regard to ancestry, family or medical leave, marital status, medical condition, physical or mental condition, political affiliation, protected veteran status, or any other legally protected characteristics. All your information will be kept confidential according to EEO guidelines.
#J-18808-Ljbffr
Your Career As a contributor in the Network Security Platform Hardware development team, you will play a key role in the complete design cycle of Palo Alto Networks Firewall and SD‑WAN hardware including selecting components, modeling and simulating memory and serdes interfaces, modeling PDN networks, defining PCB routing constraints, reviewing PCB layout, developing test plans, and performing hands‑on measurements to validate critical interfaces.
Your Impact
Collaborate with ASIC, board design, PCB layout, operations supply base management, and platform software teams.
Evaluate design trade‑offs and optimize performance, risk, cost, and manufacturability.
Contribute to ASIC package design.
Model complex 3‑dimensional structures in field‑simulation software.
Simulate channel analysis for high‑speed serdes and memory interfaces.
Design and analyze high‑speed serial links (56 Gbps and beyond) and ensure compliance with internal specs and standards.
Create and verify module/package and PCB layout rules. Perform pre‑ and post‑route signal‑integrity analysis of ASIC and multi‑chip‑module designs.
Model and analyze power delivery networks for ASIC/package/module and PCB.
Create SI test plan for coverage of all serdes, memory, and external IO interfaces.
Drive creation and implementation of test infrastructure (tools, scripts, etc.) with external vendors and internal software teams.
Perform lab measurements for design validation and simulation correlations.
Drive methodology enhancements and automation to improve performance and efficiency.
Mentor junior engineers and interns.
Qualifications
Strong background in hands‑on design and validation of high‑speed PCB and ASIC package development.
Proficient in power‑integrity design and analysis using PI simulation tools such as PowerSI/DC.
Experience with high‑speed NRZ and PAM4 serdes.
Self‑motivated with demonstrated teamwork and communication skills; ability to drive outcomes with vendors and internal teams.
Out‑of‑the‑box thinking and strong desire to innovate.
Strong EM knowledge and expertise in EM simulation tools such as HFSS, PowerDC‑SI, ADS, SiSoft.
Familiar with PCB fabrication process, dielectric material, and stack‑up design.
Solid knowledge of IEEE 802.3/OIF specifications and COM simulations.
Strong lab skills and measurement experience (VNA, TDR, real‑time scope, sampling scope, BERT).
Demonstrated troubleshooting and failure‑analysis ability.
Ability to contribute to multiple projects in a dynamic, collaborative environment.
Knowledge of optical transceivers highly desired.
The Team The engineering team is core to our mission of preventing cyberattacks. We build and innovate products that solve problems none else has tackled, constantly challenging the status quo.
Why Palo Alto Networks?
Develop NPI hardware in a creative and innovative environment.
Imagine new opportunities that impact the world.
Be part of a high‑performing team of the world's best cybersecurity companies.
Flexible work arrangements support the way you work best.
Compensation Disclosure The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non‑sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $139,000 / yr and $224,500 / yr. The offered compensation may also include restricted stock units and a bonus.
Our Commitment We’re problem solvers that take risks and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together.
Accommodations We are committed to providing reasonable accommodations for all qualified individuals. If you require assistance or accommodation due to a disability or special need, please contact us at accommodations@paloaltonetworks.com.
Equal Opportunity / EEO Palo Alto Networks is an equal opportunity employer. We celebrate an inclusive workplace and provide consideration for all qualified applicants without regard to ancestry, family or medical leave, marital status, medical condition, physical or mental condition, political affiliation, protected veteran status, or any other legally protected characteristics. All your information will be kept confidential according to EEO guidelines.
#J-18808-Ljbffr