OSI Engineering
Senior Validation Engineering Manager
OSI Engineering, San Jose, California, United States, 95199
A leading chip and silicon IP provider is hiring a Validation Manager for its Memory Interface Chip business unit.
The role includes leading and working closely with the team to validate and characterize high-performance buffer chip products. The ideal candidate will have a strong background in processor-to-memory interfaces, DDR topologies, high-speed signaling, signal integrity, and power integrity.
Responsibilities
Partner with internal and external cross-functional teams across all levels of a corporation, from executives, team managers and individual contributors including development engineers, and procurement experts
Own, develop and continuously adapt and improve validation methodologies and technologies to continuously improve design validation coverage and time-to-market
Partner with Design, Architecture, Verification, and Operation teams to deliver high-quality buffer chip products
Work with external partners in sourcing test equipment, PCB manufacturing and assembly
Lead and manage the bench validation team to execute hands‑on validation and characterization of memory buffer chips
Perform hands‑on bench validation and lab automation software development
Develop test methodologies to validate silicon designs against specifications
Qualifications
Track record of growing organizations with focus on organization and validation methodology development
Demonstrated ability with project planning, resource allocation, capital and operational budgeting and develop test methodologies for validating silicon designs against specifications
Knowledge of processor / memory device architecture and specifications
Expert on Python programming, focused on validation characterization automation, and data analysis
Experience in Bench testing, with knowledge and experience on ATE or/and System Testing is a plus
Minimum 5+ years of hands‑on bench validation experience is required
Proven experience with DDR4/DDR5 and processor/memory system architecture
Demonstrated leadership experience, either as a manager (2–5 direct reports) or as an IC with team leadership responsibilities
Education B.S. or M.S. in Electrical Engineering
Location: Atlanta, GA; San Jose, CA; United States
Salary Range: $170-$210K (DOE)
Submit resume to Jobs@OSIengineering.com
No 3rd party agencies or C2C
#J-18808-Ljbffr
The role includes leading and working closely with the team to validate and characterize high-performance buffer chip products. The ideal candidate will have a strong background in processor-to-memory interfaces, DDR topologies, high-speed signaling, signal integrity, and power integrity.
Responsibilities
Partner with internal and external cross-functional teams across all levels of a corporation, from executives, team managers and individual contributors including development engineers, and procurement experts
Own, develop and continuously adapt and improve validation methodologies and technologies to continuously improve design validation coverage and time-to-market
Partner with Design, Architecture, Verification, and Operation teams to deliver high-quality buffer chip products
Work with external partners in sourcing test equipment, PCB manufacturing and assembly
Lead and manage the bench validation team to execute hands‑on validation and characterization of memory buffer chips
Perform hands‑on bench validation and lab automation software development
Develop test methodologies to validate silicon designs against specifications
Qualifications
Track record of growing organizations with focus on organization and validation methodology development
Demonstrated ability with project planning, resource allocation, capital and operational budgeting and develop test methodologies for validating silicon designs against specifications
Knowledge of processor / memory device architecture and specifications
Expert on Python programming, focused on validation characterization automation, and data analysis
Experience in Bench testing, with knowledge and experience on ATE or/and System Testing is a plus
Minimum 5+ years of hands‑on bench validation experience is required
Proven experience with DDR4/DDR5 and processor/memory system architecture
Demonstrated leadership experience, either as a manager (2–5 direct reports) or as an IC with team leadership responsibilities
Education B.S. or M.S. in Electrical Engineering
Location: Atlanta, GA; San Jose, CA; United States
Salary Range: $170-$210K (DOE)
Submit resume to Jobs@OSIengineering.com
No 3rd party agencies or C2C
#J-18808-Ljbffr