QFocus Technologies LLC
Formal Verification Engineer
QFocus Technologies LLC, Sunnyvale, California, United States, 94087
We are seeking a highly skilled and passionate Formal Verification Engineer to join our team to work with the best in the industry, developing innovative ASIC solutions for data center and AI infrastructure. The ideal candidate will develop comprehensive formal test plans and be responsible for completing the formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC design, emulation and post-silicon teams towards creating first-pass silicon success.
Key Responsibilities
Contribute to Formal Verification by applying and evangelizing state-of-the-art Formal Verification methodologies across IP-level, subsystem-level and SOC level
Collaborate with Architecture and Design teams for the development of formal specifications and implementations.
Define Formal Verification scope, create formal environments, and achieve coverage sign-off using targeted formal verification techniques.
Develop comprehensive formal test plans, including unique security requirement verification.
Build reusable and scalable formal verification environments and deploy relevant tools.
Evaluate and recommend EDA solutions for Formal Verification and drive improvements in methodologies and flows.
Debug complex issues in RTL designs based on formal results and contribute to design improvements.
Required Skills
Strong hands-on experience with Formal Verification tools (e.g., JasperGold, VC-Formal, Questa Formal).
Experience writing formal properties using SystemVerilog Assertions (SVA) or Property Specification Language (PSL).
Proven understanding of Formal Verification methodologies, complexity reduction techniques, and abstraction techniques.
Fluency in hardware description languages such as SystemVerilog.
Proficiency in scripting languages such as Python, Perl or Tcl within Unix/Linux environments.
Education
Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.
Experience
5+ years of experience in Design Verification, with at least 1 year in Formal Verification.
We are a group of passionate and experienced technology professionals working together with a singular focus to delight our customers by delivering quantifiable value and becoming a natural extension of your team!
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Key Responsibilities
Contribute to Formal Verification by applying and evangelizing state-of-the-art Formal Verification methodologies across IP-level, subsystem-level and SOC level
Collaborate with Architecture and Design teams for the development of formal specifications and implementations.
Define Formal Verification scope, create formal environments, and achieve coverage sign-off using targeted formal verification techniques.
Develop comprehensive formal test plans, including unique security requirement verification.
Build reusable and scalable formal verification environments and deploy relevant tools.
Evaluate and recommend EDA solutions for Formal Verification and drive improvements in methodologies and flows.
Debug complex issues in RTL designs based on formal results and contribute to design improvements.
Required Skills
Strong hands-on experience with Formal Verification tools (e.g., JasperGold, VC-Formal, Questa Formal).
Experience writing formal properties using SystemVerilog Assertions (SVA) or Property Specification Language (PSL).
Proven understanding of Formal Verification methodologies, complexity reduction techniques, and abstraction techniques.
Fluency in hardware description languages such as SystemVerilog.
Proficiency in scripting languages such as Python, Perl or Tcl within Unix/Linux environments.
Education
Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.
Experience
5+ years of experience in Design Verification, with at least 1 year in Formal Verification.
We are a group of passionate and experienced technology professionals working together with a singular focus to delight our customers by delivering quantifiable value and becoming a natural extension of your team!
#J-18808-Ljbffr