Intel
Job Details
As a
Principal Microarchitecture Engineer , you will lead the definition, design, and implementation of microarchitecture for IP blocks and SoC subsystems. You will own RTL development and ensure the delivery of high‑quality, secure, and power‑efficient logic designs that meet performance, area, thermal, and timing goals.
Key Responsibilities
Microarchitecture Definition & Documentation
Define and document the microarchitecture of IP blocks or SoC components.
Deliver comprehensive Microarchitecture Specification (MAS) documents, including block diagrams, signal‑level descriptions, clocking, power, and timing requirements.
RTL Development & Design Enablement
Own RTL implementation for assigned blocks.
Decompose complex features into fundamental building blocks and guide RTL designers with clear, digestible coding tasks.
Review and coach RTL design to ensure clean partitioning and high‑quality implementation.
Design Quality & Physical Implementation
Ensure robust design through thorough documentation, design reviews, and verification support.
Direct physical design layout to meet PPA, thermal, and timing targets.
Security Integration
Apply secure development practices, addressing architecture‑level threat models and embedding security objectives into the design.
Cross‑functional Collaboration
Partner with SoC architects and cross‑functional teams to align on architecture and microarchitecture definitions.
Support post‑silicon feature enablement and drive enhancements for future product iterations.
Technical Leadership & Strategy
Serve as a recognized domain expert, influencing technical direction across Intel and the broader industry.
Mentor and develop technical leaders, foster innovation, and act as a change agent.
Align organizational goals with technical vision and formulate strategies to deliver leadership solutions.
Minimum Qualifications
Bachelor's degree in electrical engineering, Computer Engineering or related field
10+ years of proven experience in design and micro‑architecture.
Strong understanding of coherency protocols and fabric design
Proficiency in hardware description languages (HDL) such as Verilog or VHDL.
Experience with simulation and verification tools (e.g., ModelSim, VCS).
Experience using lint, CDC, and other design tools to ensure design quality.
Proficiency in static timing analysis (STA) and timing closure techniques.
Familiarity with physical design constraints and considerations.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here: https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For interns, this investigation may or may not be completed prior to starting the position.
Job Type & Location Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: US, California, Santa Clara
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Principal Microarchitecture Engineer , you will lead the definition, design, and implementation of microarchitecture for IP blocks and SoC subsystems. You will own RTL development and ensure the delivery of high‑quality, secure, and power‑efficient logic designs that meet performance, area, thermal, and timing goals.
Key Responsibilities
Microarchitecture Definition & Documentation
Define and document the microarchitecture of IP blocks or SoC components.
Deliver comprehensive Microarchitecture Specification (MAS) documents, including block diagrams, signal‑level descriptions, clocking, power, and timing requirements.
RTL Development & Design Enablement
Own RTL implementation for assigned blocks.
Decompose complex features into fundamental building blocks and guide RTL designers with clear, digestible coding tasks.
Review and coach RTL design to ensure clean partitioning and high‑quality implementation.
Design Quality & Physical Implementation
Ensure robust design through thorough documentation, design reviews, and verification support.
Direct physical design layout to meet PPA, thermal, and timing targets.
Security Integration
Apply secure development practices, addressing architecture‑level threat models and embedding security objectives into the design.
Cross‑functional Collaboration
Partner with SoC architects and cross‑functional teams to align on architecture and microarchitecture definitions.
Support post‑silicon feature enablement and drive enhancements for future product iterations.
Technical Leadership & Strategy
Serve as a recognized domain expert, influencing technical direction across Intel and the broader industry.
Mentor and develop technical leaders, foster innovation, and act as a change agent.
Align organizational goals with technical vision and formulate strategies to deliver leadership solutions.
Minimum Qualifications
Bachelor's degree in electrical engineering, Computer Engineering or related field
10+ years of proven experience in design and micro‑architecture.
Strong understanding of coherency protocols and fabric design
Proficiency in hardware description languages (HDL) such as Verilog or VHDL.
Experience with simulation and verification tools (e.g., ModelSim, VCS).
Experience using lint, CDC, and other design tools to ensure design quality.
Proficiency in static timing analysis (STA) and timing closure techniques.
Familiarity with physical design constraints and considerations.
Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation.
Find more information about all of our Amazing Benefits here: https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For interns, this investigation may or may not be completed prior to starting the position.
Job Type & Location Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: US, California, Santa Clara
#J-18808-Ljbffr