NVIDIA Corporation
ASIC Verification Engineer - New College Grad 2026
NVIDIA Corporation, Santa Clara, California, us, 95053
ASIC Verification Engineer - New College Grad 2026 page is loaded## ASIC Verification Engineer - New College Grad 2026locations:
US, CA, Santa Claratime type:
Full timeposted on:
Posted Yesterdayjob requisition id:
JR2006408NVIDIA is seeking best-in-class ASIC Verification Engineer to verify the world’s leading GPUs. In this role, you will be doing unit level verification of the process scheduling and system interface hardware of the GPU. This position will be working across many NVIDIA teams from software, to architecture, design, methodology, and more. The GPU is used in applications from consumer graphics, through self-driving cars, to artificial intelligence, all of which you will be involved in and learn about. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the methodology for verifying the future of computing.**What you’ll be doing:*** Work on a unit level testbench, working on directed and random tests and test infrastructure, and contributing to the future direction of the methodology for the testbench* Partner closely with RTL and architecture teams to help refine the microarchitecture plans to ensure that changes to the design are verifiable* Architect and plan the verification strategy and execution for sub-system features impacting your unit* Leverage state-of-the-art AI tools to improve verification efficiency, automation, and overall productivity* Support post-silicon validation activities**What we need to see:*** Recently completed a BS or MS in electrical engineering or computer engineering (or equivalent experience)* Strong communication and problem solving skills* Exposure to ASIC design, ASIC verification and computer architecture,* Strong programming and debugging capability with at least one of the following languages:
SystemVerilog, C and/or C++, Python and/or Perl* Deep knowledge of object-oriented programming concepts**Ways to stand out from the crowd:*** Experience with testplan writing and testbench component design* Exposure to constrained random testing and coverage driven verification* Exposure to verification methodology, like UVM* Background with assertion-based verification, Semiformal Verification (SFV)* Experience with AI-powered tools, like Cursor and ClaudeYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 96,000 USD - 161,000 USD for Level 1, and 108,000 USD - 184,000 USD for Level 2.You will also be eligible for equity and .Applications for this job will be accepted at least until October 30, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr
US, CA, Santa Claratime type:
Full timeposted on:
Posted Yesterdayjob requisition id:
JR2006408NVIDIA is seeking best-in-class ASIC Verification Engineer to verify the world’s leading GPUs. In this role, you will be doing unit level verification of the process scheduling and system interface hardware of the GPU. This position will be working across many NVIDIA teams from software, to architecture, design, methodology, and more. The GPU is used in applications from consumer graphics, through self-driving cars, to artificial intelligence, all of which you will be involved in and learn about. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the methodology for verifying the future of computing.**What you’ll be doing:*** Work on a unit level testbench, working on directed and random tests and test infrastructure, and contributing to the future direction of the methodology for the testbench* Partner closely with RTL and architecture teams to help refine the microarchitecture plans to ensure that changes to the design are verifiable* Architect and plan the verification strategy and execution for sub-system features impacting your unit* Leverage state-of-the-art AI tools to improve verification efficiency, automation, and overall productivity* Support post-silicon validation activities**What we need to see:*** Recently completed a BS or MS in electrical engineering or computer engineering (or equivalent experience)* Strong communication and problem solving skills* Exposure to ASIC design, ASIC verification and computer architecture,* Strong programming and debugging capability with at least one of the following languages:
SystemVerilog, C and/or C++, Python and/or Perl* Deep knowledge of object-oriented programming concepts**Ways to stand out from the crowd:*** Experience with testplan writing and testbench component design* Exposure to constrained random testing and coverage driven verification* Exposure to verification methodology, like UVM* Background with assertion-based verification, Semiformal Verification (SFV)* Experience with AI-powered tools, like Cursor and ClaudeYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 96,000 USD - 161,000 USD for Level 1, and 108,000 USD - 184,000 USD for Level 2.You will also be eligible for equity and .Applications for this job will be accepted at least until October 30, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr