TESSOLVE SEMICONDUCTOR PRIVATE LIMITED
Signal & Power Integrity (SI/PI) Engineer
TESSOLVE SEMICONDUCTOR PRIVATE LIMITED, San Jose, California, United States, 95199
About Us
Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up and spec to product. With 3200 employees worldwide, Tessolve delivers a one-stop solution with advanced silicon and system testing labs. We offer
Turnkey ASIC Solutions
from design to packaged parts, leveraging strong ecosystem partnerships with EDA, IP, and foundry vendors. Our integrated front-end and backend expertise reduces design risks and accelerates time-to-market. Our
R&D centers of excellence
focus on emerging technologies such as 5G, mmWave, Silicon Photonics, HSIO, HBM/HPI, and System-Level Test. Tessolve also delivers
end-to-end embedded product design services
under an ODM model for Avionics, Automotive, Industrial, and Medical applications. Tessolve s clientele includes
9 of the top 10 semiconductor companies , along with Tier-1 clients, start-ups, and government entities. We have a
global presence in 12 countries , with advanced
test labs in India, Singapore, Malaysia, Austin, and San Jose. For more details, visit Role: Experienced (>5y) Signal & Power Integrity Engineer to support
high-speed interfaces (LPDDR5X, PCIe Gen7, UCIe 64G) , with responsibilities extending into
power delivery network (PDN) analysis . Responsibilities
All SI tasks described above (channel modeling, extractions, eye analysis). Perform
power integrity extractions and simulations
for high-speed interfaces. Model and analyze
package/board PDN Define decoupling strategy and validate against system requirements. Provide design guidelines balancing both
SI and PI constraints . Qualifications
Strong background in
both signal and power integrity . Hands-on experience with SI tools (listed above). Proficiency with
PI extraction/simulation tools
(e.g., PowerSI, SIwave, AEDT, HSPICE, equivalent). Knowledge of DDR, PCIe, UCIe standards and PDN design best practices. Strong analytical and communication skills. Why Tessolve
Join a global semiconductor solutions leader, where you ll work on
cutting-edge packaging design
projects across advanced technologies, collaborate with
world-class engineering teams , and help shape the future of semiconductor innovation. Equal Opportunity Employer
Tessolve is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment
without regard to race, color, religion, gender, sexual orientation, national origin, age, disability, veteran status, or any other protected characteristic.
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Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up and spec to product. With 3200 employees worldwide, Tessolve delivers a one-stop solution with advanced silicon and system testing labs. We offer
Turnkey ASIC Solutions
from design to packaged parts, leveraging strong ecosystem partnerships with EDA, IP, and foundry vendors. Our integrated front-end and backend expertise reduces design risks and accelerates time-to-market. Our
R&D centers of excellence
focus on emerging technologies such as 5G, mmWave, Silicon Photonics, HSIO, HBM/HPI, and System-Level Test. Tessolve also delivers
end-to-end embedded product design services
under an ODM model for Avionics, Automotive, Industrial, and Medical applications. Tessolve s clientele includes
9 of the top 10 semiconductor companies , along with Tier-1 clients, start-ups, and government entities. We have a
global presence in 12 countries , with advanced
test labs in India, Singapore, Malaysia, Austin, and San Jose. For more details, visit Role: Experienced (>5y) Signal & Power Integrity Engineer to support
high-speed interfaces (LPDDR5X, PCIe Gen7, UCIe 64G) , with responsibilities extending into
power delivery network (PDN) analysis . Responsibilities
All SI tasks described above (channel modeling, extractions, eye analysis). Perform
power integrity extractions and simulations
for high-speed interfaces. Model and analyze
package/board PDN Define decoupling strategy and validate against system requirements. Provide design guidelines balancing both
SI and PI constraints . Qualifications
Strong background in
both signal and power integrity . Hands-on experience with SI tools (listed above). Proficiency with
PI extraction/simulation tools
(e.g., PowerSI, SIwave, AEDT, HSPICE, equivalent). Knowledge of DDR, PCIe, UCIe standards and PDN design best practices. Strong analytical and communication skills. Why Tessolve
Join a global semiconductor solutions leader, where you ll work on
cutting-edge packaging design
projects across advanced technologies, collaborate with
world-class engineering teams , and help shape the future of semiconductor innovation. Equal Opportunity Employer
Tessolve is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment
without regard to race, color, religion, gender, sexual orientation, national origin, age, disability, veteran status, or any other protected characteristic.
#J-18808-Ljbffr