Nokia
Sr Principal Analog Mixed-Signal Design Engineer
Nokia, San Francisco, California, United States, 94199
Job Description
.Design, implement, and simulate the functionality and performance of high resolution data-converters including DACs and ADCs; .Design, implement, and simulate the functionality and performance of other various low power, low noise analog circuits such as band-gap and reference circuits, opamps and output buffers; .Craft layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands-on in drawing layout if necessary; .Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality; .Need to comply with the team's design methodologies and release flows.
Responsibilities
Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Layout and Layout-XL, Mentor AFS and Calibre. Must have a proven tracking record of designing data-converters and taking them to production; Must have a good understanding of standard CMOS as well as high-voltage technologies (e.g. BCD) analog / mixed-signal design methodologies and circuit analysis; Must have a good understanding of ESD protections; Must have a good understanding of device physics and the impacts of layout effects; Able to perform the behavioral modeling of the blocks and circuits with Verilog-A or Verilog-AMS; Collaborative with other local or remote team members in a professional environment.
Qualifications
Fluent in verbal and written communications; Capable of coaching and mentoring new or junior circuit designers and layout engineers; Independently resolves issues and conquers design challenges; Self-motivated and detail-oriented.
Education and Experience Requirements:
Staff Design Engineer: M.S. in E.E. with 8+ years experience, or Ph.D. in E.E. with 8+ years experience Principal Design Engineer: M.S. in E.E. with 12+ years experience, or Ph.D. in E.E. with 12+ years experience
.Design, implement, and simulate the functionality and performance of high resolution data-converters including DACs and ADCs; .Design, implement, and simulate the functionality and performance of other various low power, low noise analog circuits such as band-gap and reference circuits, opamps and output buffers; .Craft layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands-on in drawing layout if necessary; .Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality; .Need to comply with the team's design methodologies and release flows.
Responsibilities
Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Layout and Layout-XL, Mentor AFS and Calibre. Must have a proven tracking record of designing data-converters and taking them to production; Must have a good understanding of standard CMOS as well as high-voltage technologies (e.g. BCD) analog / mixed-signal design methodologies and circuit analysis; Must have a good understanding of ESD protections; Must have a good understanding of device physics and the impacts of layout effects; Able to perform the behavioral modeling of the blocks and circuits with Verilog-A or Verilog-AMS; Collaborative with other local or remote team members in a professional environment.
Qualifications
Fluent in verbal and written communications; Capable of coaching and mentoring new or junior circuit designers and layout engineers; Independently resolves issues and conquers design challenges; Self-motivated and detail-oriented.
Education and Experience Requirements:
Staff Design Engineer: M.S. in E.E. with 8+ years experience, or Ph.D. in E.E. with 8+ years experience Principal Design Engineer: M.S. in E.E. with 12+ years experience, or Ph.D. in E.E. with 12+ years experience