DFT Verification Engineer

Key Responsibilities: Perform DFT verification using Mentor Tessent (LogicBIST, MBIST, SSN). Verify scan structures and test logic at the full-chip and multi-die level. Collaborate with design and DFT teams to ensure coverage, debug, and flow integrity. Contribute to validation and bring-up of complex SoCs. Top Skills manager is looking for: Recent Tessent (Siemens/Mentor) hands‑on experience (SSN/ Scan Steam Network experience ideal). Strong DFT Verification background (not just ATPG/scan). Full-chip verification experience. Multi-die or chiplet experience preferred.

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