Energy Jobline ZR
Ethernet ASIC Design Engineer in San Jose
Energy Jobline ZR, San Jose, California, United States, 95199
Job Summary
Cornelis Networks delivers the world’s highest performance scale‑out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software, and system‑level technologies to maximize the efficiency of GPU, CPU, and accelerator‑based compute clusters at any scale. We are a fast‑growing, forward‑thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies across the United States and six other countries, offering onsite, hybrid, and fully remote roles.
Key Responsibilities
Design and implement advanced Ethernet protocols for next‑generation Ethernet switch ASICs, focusing on RTL development.
Develop microarchitecture specifications for Ethernet protocol blocks.
Implement Ethernet protocols such as Priority Flow Control, TCP, UDP, RoCEv2, VLAN, ECMP, DCQCN, ECN, and security in transmit and receive pipelines using Verilog/System Verilog.
Collaborate with verification engineers to create block‑ and system‑level test plans to ensure comprehensive design coverage.
Define timing constraints for RTL blocks and work with physical design engineers to optimize timing closure.
Support post‑silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
Contribute to performance optimization and power‑aware design strategies for Ethernet subsystems.
Minimum Qualifications
B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field.
10+ years of industry experience in digital design with proficiency in Verilog and System Verilog.
Experience in RTL design for Ethernet protocols relevant to adapters and switches.
Familiarity with timing closure and modern physical design methodologies.
Proven ability in system‑level debug and root cause analysis of technical issues.
Strong verbal and written communication skills.
Qualifications
Deep knowledge of Ethernet architecture and networking protocols (L2/L3/L4 layers).
Prior experience with Ethernet MAC integration and development of L2/L3/L4 protocols for ASICs, including system debug.
Expertise in multiple clock domain designs and asynchronous interfaces.
10+ years of experience with scripting such as TCL, Python, or Perl.
Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime.
Location This is a remote position for employees residing within the United States.
Compensation and Benefits We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry. Benefits include medical, dental, and vision coverage, life insurance, a dependent care flexible spending account, accidental injury insurance, pet insurance, generous paid holidays, 401(k) with company match, and open time off for regular full‑time exempt employees.
Equal Opportunity Employer Cornelis Networks is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, gender identity, sexual orientation, national origin, age, disability, veteran status, or genetic information.
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Key Responsibilities
Design and implement advanced Ethernet protocols for next‑generation Ethernet switch ASICs, focusing on RTL development.
Develop microarchitecture specifications for Ethernet protocol blocks.
Implement Ethernet protocols such as Priority Flow Control, TCP, UDP, RoCEv2, VLAN, ECMP, DCQCN, ECN, and security in transmit and receive pipelines using Verilog/System Verilog.
Collaborate with verification engineers to create block‑ and system‑level test plans to ensure comprehensive design coverage.
Define timing constraints for RTL blocks and work with physical design engineers to optimize timing closure.
Support post‑silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
Contribute to performance optimization and power‑aware design strategies for Ethernet subsystems.
Minimum Qualifications
B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field.
10+ years of industry experience in digital design with proficiency in Verilog and System Verilog.
Experience in RTL design for Ethernet protocols relevant to adapters and switches.
Familiarity with timing closure and modern physical design methodologies.
Proven ability in system‑level debug and root cause analysis of technical issues.
Strong verbal and written communication skills.
Qualifications
Deep knowledge of Ethernet architecture and networking protocols (L2/L3/L4 layers).
Prior experience with Ethernet MAC integration and development of L2/L3/L4 protocols for ASICs, including system debug.
Expertise in multiple clock domain designs and asynchronous interfaces.
10+ years of experience with scripting such as TCL, Python, or Perl.
Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime.
Location This is a remote position for employees residing within the United States.
Compensation and Benefits We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry. Benefits include medical, dental, and vision coverage, life insurance, a dependent care flexible spending account, accidental injury insurance, pet insurance, generous paid holidays, 401(k) with company match, and open time off for regular full‑time exempt employees.
Equal Opportunity Employer Cornelis Networks is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, gender identity, sexual orientation, national origin, age, disability, veteran status, or genetic information.
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