Salt
Salt is proud to partner with a leading global technology company in search of a
Mask Layout Designer
to join their world‑class AMS team.
In this role, you’ll collaborate with highly skilled design and layout engineers to develop cutting‑edge System‑on‑Chip (SoC) components.
You’ll be responsible for delivering fully verified analog and mixed‑signal layouts, ensuring top performance, precision, and reliability.
What You’ll Do:
Design and optimize complex layouts for analog and mixed‑signal circuits in deep sub‑micron CMOS and FinFET technologies.
Analyze detailed schematics and floorplans, identifying layout trade‑offs and ensuring compliance with design specifications.
Run and interpret verification reports (LVS, DRC, ERC) using industry‑standard tools.
Apply CAD expertise and automation skills to deliver accurate, high‑quality layouts that meet power, area, and performance goals.
Collaborate cross‑functionally with circuit design, CAD, and verification teams to drive efficient project execution and innovation.
Who You Are:
6+ years of experience in analog/mixed‑signal layout design.
Proven experience in layout design of tight matching, low‑noise, and low‑power analog blocks, including resistors, capacitors, pad IOs, and ESD structures.
Skilled in addressing IR drop, RC delay, electromigration, self‑heating, and cross‑capacitance challenges.
Hands‑on experience with CALIBRE DRC, ERC, and LVS reports.
Deep understanding of analog/mixed‑signal layout design in submicron CMOS and FinFET processes.
Familiar with Virtuoso, Innovus, and related CAD tools.
Programming knowledge in SKILL, Perl, or Python is a plus.
Bachelor’s or Master’s degree in Electrical or Electronic Engineering (or related field).
Comfortable working on macOS and iOS platforms.
Excellent communicator who thrives in collaborative, fast‑paced environments.
Seniority Level Mid‑Senior level
Employment Type Contract
Job Function Design and Engineering
#J-18808-Ljbffr
Mask Layout Designer
to join their world‑class AMS team.
In this role, you’ll collaborate with highly skilled design and layout engineers to develop cutting‑edge System‑on‑Chip (SoC) components.
You’ll be responsible for delivering fully verified analog and mixed‑signal layouts, ensuring top performance, precision, and reliability.
What You’ll Do:
Design and optimize complex layouts for analog and mixed‑signal circuits in deep sub‑micron CMOS and FinFET technologies.
Analyze detailed schematics and floorplans, identifying layout trade‑offs and ensuring compliance with design specifications.
Run and interpret verification reports (LVS, DRC, ERC) using industry‑standard tools.
Apply CAD expertise and automation skills to deliver accurate, high‑quality layouts that meet power, area, and performance goals.
Collaborate cross‑functionally with circuit design, CAD, and verification teams to drive efficient project execution and innovation.
Who You Are:
6+ years of experience in analog/mixed‑signal layout design.
Proven experience in layout design of tight matching, low‑noise, and low‑power analog blocks, including resistors, capacitors, pad IOs, and ESD structures.
Skilled in addressing IR drop, RC delay, electromigration, self‑heating, and cross‑capacitance challenges.
Hands‑on experience with CALIBRE DRC, ERC, and LVS reports.
Deep understanding of analog/mixed‑signal layout design in submicron CMOS and FinFET processes.
Familiar with Virtuoso, Innovus, and related CAD tools.
Programming knowledge in SKILL, Perl, or Python is a plus.
Bachelor’s or Master’s degree in Electrical or Electronic Engineering (or related field).
Comfortable working on macOS and iOS platforms.
Excellent communicator who thrives in collaborative, fast‑paced environments.
Seniority Level Mid‑Senior level
Employment Type Contract
Job Function Design and Engineering
#J-18808-Ljbffr