Ayar Labs
Director of SoC / ASIC Integration
Ayar Labs is seeking a Director of SoC / ASIC integration to develop and tape out the next generation of electronic-photonic integrated chips. The candidate will be responsible for leading the ASIC integration team, performing design integration, physical design, and tapeouts of ICs containing custom analog, photonic, and digital subsystems implemented in both 3DIC and specialty platforms. The ideal candidate will be a mission-driven team leader with management and leadership experience in product-focused organizations, with a comprehensive silicon development background, a track record of first-silicon successes, and eagerness to apply specialized ASIC skillsets to a wide range of problems.
Essential Functions: Manage and grow the skillsets of an experienced ASIC integration team which has successfully taped out multiple generations of Ayar Labs SoCs Drive timely execution of both test chip and product tapeouts Develop and improve upon complex SoC integration flows integrating photonics, circuits, advanced nodes, and 3DIC integration in leading edge nodes Oversee digital-top physical design and RTL2GDS flows: synthesis, place and route, and static timing analysis Drive clear and effective decision-making across multiple functions and teams within the organization Implement SoC signoff and cross-check methodologies to deliver high-quality tapeouts incorporating a wide range of disciplines Maintain EDA infrastructure for the broader design organization Basic Qualifications:
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related fields 10+ years of experience in ASIC development and tapeouts 5+ years of Experience leading teams of both local and remote engineers through successful tapeouts in multiple leading edge technologies Experience driving tool and IP vendor evaluation and selection Strong problem solving skills and demonstrated ability to apply known methodologies towards new problems Expert in a broad set of ASIC flows and methodologies: RTL2GDS, EMIR, DFT, STA, LVS, DRC, LIB/LEF Experience working with integration of analog and digital components into SoC's Passionate about developing and enhancing build flows, methodologies, and automation Strong communicator and team-builder who can drive cross-functional alignment Preferred Qualifications:
Experience with design or implementation of SerDes IP block interfaces in a complex SoC fabric environment Experience working through issues in speciality or immature process technologies Core knowledge of semiconductor physics Working knowledge of optics and silicon photonics
Salary range: $220,000 - $275,000
NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.
About Ayar Labs:
At Ayar Labs we're about to revolutionize computing by moving data with light. We're unleashing processing power for artificial intelligence, high performance computing, cloud and telecommunications by removing the bottlenecks created by today's electrical I/O -- making it possible to continue scaling computing system performance. Ayar Labs is the first to deliver an optical I/O solution that combines in-package optical I/O chiplets and multi-wavelength remote light sources to replace traditional electrical I/O. This silicon photonics-based I/O solution enables chips to communicate with each other from millimeters to kilometers, to deliver orders of magnitude improvements in latency, bandwidth density, and power consumption. With our strong collaborations with industry leaders and government, our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and electronics, joining our team gives you the opportunity to collaborate with renowned experts on challenging, paradigm-shifting work. We are passionate about delivering in-package optical I/O at scale, leveraging the strength of our patent portfolio and our team of leading interdisciplinary experts. We believe that deep cross-collaboration between teams facilitated by honest, open debate is the best way to drive innovation and achieve big wins. Join our team and experience the possibilities. Resources: Executives from Intel and GLOBALFOUNDRIES share their thoughts on Ayar Labs and the promise of in-package optical I/O (video) Ayar Labs in the News and Recent announcements LinkedIn and Twitter
Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.
Ayar Labs is seeking a Director of SoC / ASIC integration to develop and tape out the next generation of electronic-photonic integrated chips. The candidate will be responsible for leading the ASIC integration team, performing design integration, physical design, and tapeouts of ICs containing custom analog, photonic, and digital subsystems implemented in both 3DIC and specialty platforms. The ideal candidate will be a mission-driven team leader with management and leadership experience in product-focused organizations, with a comprehensive silicon development background, a track record of first-silicon successes, and eagerness to apply specialized ASIC skillsets to a wide range of problems.
Essential Functions: Manage and grow the skillsets of an experienced ASIC integration team which has successfully taped out multiple generations of Ayar Labs SoCs Drive timely execution of both test chip and product tapeouts Develop and improve upon complex SoC integration flows integrating photonics, circuits, advanced nodes, and 3DIC integration in leading edge nodes Oversee digital-top physical design and RTL2GDS flows: synthesis, place and route, and static timing analysis Drive clear and effective decision-making across multiple functions and teams within the organization Implement SoC signoff and cross-check methodologies to deliver high-quality tapeouts incorporating a wide range of disciplines Maintain EDA infrastructure for the broader design organization Basic Qualifications:
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related fields 10+ years of experience in ASIC development and tapeouts 5+ years of Experience leading teams of both local and remote engineers through successful tapeouts in multiple leading edge technologies Experience driving tool and IP vendor evaluation and selection Strong problem solving skills and demonstrated ability to apply known methodologies towards new problems Expert in a broad set of ASIC flows and methodologies: RTL2GDS, EMIR, DFT, STA, LVS, DRC, LIB/LEF Experience working with integration of analog and digital components into SoC's Passionate about developing and enhancing build flows, methodologies, and automation Strong communicator and team-builder who can drive cross-functional alignment Preferred Qualifications:
Experience with design or implementation of SerDes IP block interfaces in a complex SoC fabric environment Experience working through issues in speciality or immature process technologies Core knowledge of semiconductor physics Working knowledge of optics and silicon photonics
Salary range: $220,000 - $275,000
NOTE TO RECRUITERS: Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.
About Ayar Labs:
At Ayar Labs we're about to revolutionize computing by moving data with light. We're unleashing processing power for artificial intelligence, high performance computing, cloud and telecommunications by removing the bottlenecks created by today's electrical I/O -- making it possible to continue scaling computing system performance. Ayar Labs is the first to deliver an optical I/O solution that combines in-package optical I/O chiplets and multi-wavelength remote light sources to replace traditional electrical I/O. This silicon photonics-based I/O solution enables chips to communicate with each other from millimeters to kilometers, to deliver orders of magnitude improvements in latency, bandwidth density, and power consumption. With our strong collaborations with industry leaders and government, our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and electronics, joining our team gives you the opportunity to collaborate with renowned experts on challenging, paradigm-shifting work. We are passionate about delivering in-package optical I/O at scale, leveraging the strength of our patent portfolio and our team of leading interdisciplinary experts. We believe that deep cross-collaboration between teams facilitated by honest, open debate is the best way to drive innovation and achieve big wins. Join our team and experience the possibilities. Resources: Executives from Intel and GLOBALFOUNDRIES share their thoughts on Ayar Labs and the promise of in-package optical I/O (video) Ayar Labs in the News and Recent announcements LinkedIn and Twitter
Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.