TPI Global Solutions
Senior Verification Engineer – AMD
AMD is searching for a Senior Verification Engineer to join their team in Longmont, CO, for a 1-year contract with a possible extension. Ideal candidate is experienced
RTL verification experience, Verilog/System Verilog, Modelsim/VCS, UVM.
Location: Longmont, CO – 100% onsite.
Employment type: Contract
Job Duties
Participate in design and functional verification of a block(s) of IP. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block and overall system.
Be responsible for developing and improving simulation test environments consisting of directed and constrained-random tests to be run during simulation.
Adopt the evolving verification methodologies used in the industry to functionally and work within the existing verification infrastructure.
Be familiar with hardware modeling and/or assertion-based verification methods.
Qualifications
8 or more years of proven verification experience on Verilog and System Verilog for IP development and verification.
Familiar with UVM verification methodologies and environments.
Experience with simulation tools ModelSim/VCS and VIPs.
Experience in Verilog/SystemVerilog.
Strong analytical skills and attention to detail.
Excellent written and communication skills.
Familiarity with PCIe and serial protocols is a bonus.
AMD/Xilinx FPGA and tools experience is a bonus.
Benefits
Medical insurance
Vision insurance
Disability insurance
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RTL verification experience, Verilog/System Verilog, Modelsim/VCS, UVM.
Location: Longmont, CO – 100% onsite.
Employment type: Contract
Job Duties
Participate in design and functional verification of a block(s) of IP. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block and overall system.
Be responsible for developing and improving simulation test environments consisting of directed and constrained-random tests to be run during simulation.
Adopt the evolving verification methodologies used in the industry to functionally and work within the existing verification infrastructure.
Be familiar with hardware modeling and/or assertion-based verification methods.
Qualifications
8 or more years of proven verification experience on Verilog and System Verilog for IP development and verification.
Familiar with UVM verification methodologies and environments.
Experience with simulation tools ModelSim/VCS and VIPs.
Experience in Verilog/SystemVerilog.
Strong analytical skills and attention to detail.
Excellent written and communication skills.
Familiarity with PCIe and serial protocols is a bonus.
AMD/Xilinx FPGA and tools experience is a bonus.
Benefits
Medical insurance
Vision insurance
Disability insurance
#J-18808-Ljbffr