Talently
Substrate IC Package Layout Design Engineer
Talently, San Jose, California, United States, 95199
Substrate IC Package Layout Design Engineer
Join a pioneering team in the software and hardware acceleration sector that is redefining AI infrastructure by creating custom ASICs purpose-built for transformer models. This is your opportunity to drive end-to-end IC package substrate design for next-generation AI inference systems that enable unprecedented speed and capability.
Base pay range $210,000.00/yr - $300,000.00/yr
Location On Site - San Jose, California, United States
Skills IC Substrate Packages, High Speed Signaling, Pre-Silicon Validation, Signal Integrity, Allegro Package Designer
Responsibilities
Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators.
Design large (>50mm), multi-layer substrate packages with high pin counts and dense routing to meet demanding performance requirements.
Engineer robust power delivery networks supporting >700W custom silicon solutions for advanced ASICs.
Develop high-speed signal routing capable of >50GHz operation, minimizing signal integrity issues such as crosstalk and loss.
Collaborate cross-functionally with silicon, system, SI/PI, and packaging engineers to meet co-design and integration benchmarks.
Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for both thermal and electrical performance, ensuring manufacturability with OSAT partners.
Perform rigorous DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate layouts.
Document design processes, support technical reviews, and mentor junior team members on best practices.
Must-Have Skills
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
10+ years of experience in IC substrate layout design for high-performance processors or accelerators.
Proven expertise with large substrate packages (>50mm) and high-density, multi-layer layouts.
Extensive experience with high-power (>700W) package designs and advanced power delivery networks.
Mastery of Allegro Package Designer for constraint management, layout, routing, and verification.
Deep understanding of high-speed signaling (>50GHz) and ability to solve signal integrity/power integrity challenges.
Strong collaboration skills in cross-functional engineering environments.
Familiarity with OSAT manufacturing processes and design-for-manufacturability (DFM) best practices.
Hands-on background with pre-silicon validation tools and methodologies.
Expertise in documenting design guidelines and mentoring junior engineers.
Exposure to continuous, high-iteration start-up environments or fast-paced tech sectors.
Seniority level Mid-Senior level
Employment type Full-time
Job function Software Development
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Base pay range $210,000.00/yr - $300,000.00/yr
Location On Site - San Jose, California, United States
Skills IC Substrate Packages, High Speed Signaling, Pre-Silicon Validation, Signal Integrity, Allegro Package Designer
Responsibilities
Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators.
Design large (>50mm), multi-layer substrate packages with high pin counts and dense routing to meet demanding performance requirements.
Engineer robust power delivery networks supporting >700W custom silicon solutions for advanced ASICs.
Develop high-speed signal routing capable of >50GHz operation, minimizing signal integrity issues such as crosstalk and loss.
Collaborate cross-functionally with silicon, system, SI/PI, and packaging engineers to meet co-design and integration benchmarks.
Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for both thermal and electrical performance, ensuring manufacturability with OSAT partners.
Perform rigorous DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate layouts.
Document design processes, support technical reviews, and mentor junior team members on best practices.
Must-Have Skills
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
10+ years of experience in IC substrate layout design for high-performance processors or accelerators.
Proven expertise with large substrate packages (>50mm) and high-density, multi-layer layouts.
Extensive experience with high-power (>700W) package designs and advanced power delivery networks.
Mastery of Allegro Package Designer for constraint management, layout, routing, and verification.
Deep understanding of high-speed signaling (>50GHz) and ability to solve signal integrity/power integrity challenges.
Strong collaboration skills in cross-functional engineering environments.
Familiarity with OSAT manufacturing processes and design-for-manufacturability (DFM) best practices.
Hands-on background with pre-silicon validation tools and methodologies.
Expertise in documenting design guidelines and mentoring junior engineers.
Exposure to continuous, high-iteration start-up environments or fast-paced tech sectors.
Seniority level Mid-Senior level
Employment type Full-time
Job function Software Development
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