Astera Labs
Distinguished Product Quality Engineer
Astera Labs, San Jose, California, United States, 95199
Overview
Distinguished Product Quality Engineer
at
Astera Labs Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up and scale-out connectivity. Discover more at www.asteralabs.com.
Responsibilities
Drive Product Quality Engineering across NPI and volume manufacturing for high-speed (SerDes PAM4 and optical-integrated) semiconductor products from design through high-volume production.
Serve as the primary quality interface for IC NPI activities: assess test coverage, design quality risks, and other NPI quality considerations.
Lead development and implementation of IC diagnostic test strategies; define diagnostic coverage metrics; collaborate with internal teams to enable robust debug methodologies across process technologies (16nm to
Lead debugging of complex hardware, firmware, and software issues; develop and maintain automated diagnostic tools; improve diagnostic efficiency and product yield; integrate diagnostics into silicon lifecycle management, firmware release, and reliability tracking.
Ensure interoperability, diagnostic transparency, and robust field debug capability across field, firmware, and internal engineering teams.
Define and deploy diagnostic test plans, fixtures, tools, and methodologies for fault isolation of customer returns in PCIe, CXL, UCIe, Ethernet, and other high-speed switching products; extend tools to broader NPI qualification and field issues.
Champion embedded silicon agents monitoring temperature, voltage, noise, process, timing, etc., at the block level on-chip; collaborate with design, validation, and firmware/software teams to enable real-time adaptive behavior and actionable conclusions.
Drive early Design-for-Testability (DFT) and diagnostic capabilities; coordinate block-by-block reviews to ensure coverage and apply lessons learned.
Develop diagnostic methodologies for advanced packaging (MCM, 3DIC, optical) and heterogeneous integration to diagnose and ensure high-quality products.
Skills & Experience
Deep experience with digital and SerDes high-speed protocols (PCIe Gen5/Gen6, CXL, UCIe, Ethernet/SerDes) and system-level validation methodologies.
Experience with embedded silicon diagnostic agents and product characterization/test plans; ability to analyze data across process, voltage, and temperature.
Hands-on lab debugging tools experience (protocol analyzers, oscilloscopes, BERTs, error injection frameworks).
Proficiency in scripting/software development (Python, C/C++, Java, or similar) for diagnostic automation and data analysis.
Ability to analyze complex test data, identify root causes, and implement systemic improvements.
Familiarity with semiconductor test flows (ATE, system-level test, characterization, production validation).
Experience with advanced packaging technologies (MCM, 3DIC, optical) and their diagnostic/test challenges.
Strong communication skills for cross-functional collaboration and influencing decisions to improve product quality.
Preferred Qualifications
Minimum of 5 years leading a high-caliber product engineering team.
Minimum of 10 years in product or diagnostics engineering with successful deployment of semiconductor devices into production.
Bachelor’s degree in Electrical Engineering; Master’s preferred. Experience with diagnostic firmware and test development methodologies.
Knowledge of anomaly detection techniques in diagnostic/test data.
Track record of leadership in new product introduction (NPI) for complex, high-speed semiconductor products.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Job Details
Seniority level: Mid-Senior level
Employment type: Full-time
Job function: Quality Assurance
Industries: Semiconductor Manufacturing
Referrals increase your chances of interviewing at Astera Labs. Get notified about new Product Quality Engineer jobs in San Jose, CA.
Locations with reported compensation ranges include: Sunnyvale, San Jose, Fremont, Santa Clara, Mountain View, Newark, Palo Alto, and others. Example ranges shown in job postings vary by location.
We are an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.
#J-18808-Ljbffr
Distinguished Product Quality Engineer
at
Astera Labs Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up and scale-out connectivity. Discover more at www.asteralabs.com.
Responsibilities
Drive Product Quality Engineering across NPI and volume manufacturing for high-speed (SerDes PAM4 and optical-integrated) semiconductor products from design through high-volume production.
Serve as the primary quality interface for IC NPI activities: assess test coverage, design quality risks, and other NPI quality considerations.
Lead development and implementation of IC diagnostic test strategies; define diagnostic coverage metrics; collaborate with internal teams to enable robust debug methodologies across process technologies (16nm to
Lead debugging of complex hardware, firmware, and software issues; develop and maintain automated diagnostic tools; improve diagnostic efficiency and product yield; integrate diagnostics into silicon lifecycle management, firmware release, and reliability tracking.
Ensure interoperability, diagnostic transparency, and robust field debug capability across field, firmware, and internal engineering teams.
Define and deploy diagnostic test plans, fixtures, tools, and methodologies for fault isolation of customer returns in PCIe, CXL, UCIe, Ethernet, and other high-speed switching products; extend tools to broader NPI qualification and field issues.
Champion embedded silicon agents monitoring temperature, voltage, noise, process, timing, etc., at the block level on-chip; collaborate with design, validation, and firmware/software teams to enable real-time adaptive behavior and actionable conclusions.
Drive early Design-for-Testability (DFT) and diagnostic capabilities; coordinate block-by-block reviews to ensure coverage and apply lessons learned.
Develop diagnostic methodologies for advanced packaging (MCM, 3DIC, optical) and heterogeneous integration to diagnose and ensure high-quality products.
Skills & Experience
Deep experience with digital and SerDes high-speed protocols (PCIe Gen5/Gen6, CXL, UCIe, Ethernet/SerDes) and system-level validation methodologies.
Experience with embedded silicon diagnostic agents and product characterization/test plans; ability to analyze data across process, voltage, and temperature.
Hands-on lab debugging tools experience (protocol analyzers, oscilloscopes, BERTs, error injection frameworks).
Proficiency in scripting/software development (Python, C/C++, Java, or similar) for diagnostic automation and data analysis.
Ability to analyze complex test data, identify root causes, and implement systemic improvements.
Familiarity with semiconductor test flows (ATE, system-level test, characterization, production validation).
Experience with advanced packaging technologies (MCM, 3DIC, optical) and their diagnostic/test challenges.
Strong communication skills for cross-functional collaboration and influencing decisions to improve product quality.
Preferred Qualifications
Minimum of 5 years leading a high-caliber product engineering team.
Minimum of 10 years in product or diagnostics engineering with successful deployment of semiconductor devices into production.
Bachelor’s degree in Electrical Engineering; Master’s preferred. Experience with diagnostic firmware and test development methodologies.
Knowledge of anomaly detection techniques in diagnostic/test data.
Track record of leadership in new product introduction (NPI) for complex, high-speed semiconductor products.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Job Details
Seniority level: Mid-Senior level
Employment type: Full-time
Job function: Quality Assurance
Industries: Semiconductor Manufacturing
Referrals increase your chances of interviewing at Astera Labs. Get notified about new Product Quality Engineer jobs in San Jose, CA.
Locations with reported compensation ranges include: Sunnyvale, San Jose, Fremont, Santa Clara, Mountain View, Newark, Palo Alto, and others. Example ranges shown in job postings vary by location.
We are an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, or disability.
#J-18808-Ljbffr