Scalence L.L.C.
Embedded Firmware Test Engineer (Entry level)
Scalence L.L.C., San Jose, California, United States, 95199
Embedded Firmware Test Engineer (Entry level)
Do something big and innovative! Stretch your creative muscles and work on big issues. Since 1989, we have developed technology environments, applications, and tools by providing experienced teams to implement, enhance, and maintain our clients’ essential systems and applications. Come join the Scalence team! Location:
San Jose, CA Engagement:
12 months+ Pay:
$45/hr. W2 incl. benefits Overview
This team is developing a reference design for our next gen of glasses. Responsibilities
Pre-silicon FPGA and Post-Silicon ASIC firmware validation. Define and develop tests based on vendor-provided SDKs for functional validation and power characterization. Develop automated test/regression environments based on vendor-provided tests. Develop targeted tests to reproduce reported issues. Deliverables
Test Plan Coverage on FPGA and ASIC: Run vendor-provided tests and establish a baseline on the FPGA. Augment vendor-provided tests to improve coverage of P0 product features on FPGA and ASIC. Support this activity through various hardware and software releases. Track and drive resolution of potential instabilities. Power Measurements and Optimization: Work on EVBs and form-factor devices based on the ASICs to measure and optimize power. Develop dashboards to help track power regressions. Create automated test environments based on the vendor-provided tests and XR team’s tests. Track, triage, and resolve regressions. Candidates must possess
Bachelors or Masters in Electrical Engineering and/or Computer Science with a minimum of 3 years of experience in a similar role. Working proficiency in Linux (mandatory). Readability in C, C++, and Python. Experience with scripting. Familiarity with RTOS-based systems. Experience working with potentially unstable hardware/software under development. Lab experience: Working with oscilloscopes, logic analyzers, etc. Nice to have
Experience with FPGAs, board design, low-speed interface protocols (I2C, SPI, UART), and MIPI. Recruiter Contact
Recruiter Name: Jolly Jayaprakash Contact Email/Phone: jolly.jayaprakash@scalence.com | 480-845-3303 scalence.com Referrals welcome! Referral bonus up to $1000. Feel free to reach out for additional details.
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Do something big and innovative! Stretch your creative muscles and work on big issues. Since 1989, we have developed technology environments, applications, and tools by providing experienced teams to implement, enhance, and maintain our clients’ essential systems and applications. Come join the Scalence team! Location:
San Jose, CA Engagement:
12 months+ Pay:
$45/hr. W2 incl. benefits Overview
This team is developing a reference design for our next gen of glasses. Responsibilities
Pre-silicon FPGA and Post-Silicon ASIC firmware validation. Define and develop tests based on vendor-provided SDKs for functional validation and power characterization. Develop automated test/regression environments based on vendor-provided tests. Develop targeted tests to reproduce reported issues. Deliverables
Test Plan Coverage on FPGA and ASIC: Run vendor-provided tests and establish a baseline on the FPGA. Augment vendor-provided tests to improve coverage of P0 product features on FPGA and ASIC. Support this activity through various hardware and software releases. Track and drive resolution of potential instabilities. Power Measurements and Optimization: Work on EVBs and form-factor devices based on the ASICs to measure and optimize power. Develop dashboards to help track power regressions. Create automated test environments based on the vendor-provided tests and XR team’s tests. Track, triage, and resolve regressions. Candidates must possess
Bachelors or Masters in Electrical Engineering and/or Computer Science with a minimum of 3 years of experience in a similar role. Working proficiency in Linux (mandatory). Readability in C, C++, and Python. Experience with scripting. Familiarity with RTOS-based systems. Experience working with potentially unstable hardware/software under development. Lab experience: Working with oscilloscopes, logic analyzers, etc. Nice to have
Experience with FPGAs, board design, low-speed interface protocols (I2C, SPI, UART), and MIPI. Recruiter Contact
Recruiter Name: Jolly Jayaprakash Contact Email/Phone: jolly.jayaprakash@scalence.com | 480-845-3303 scalence.com Referrals welcome! Referral bonus up to $1000. Feel free to reach out for additional details.
#J-18808-Ljbffr