Mogi I/O : OTT/Podcast/Short Video Apps for you
ASIC RTL Design Engineer – Semiconductor Development
Mogi I/O : OTT/Podcast/Short Video Apps for you, Austin, Texas, us, 78716
Job Overview
Seeking an experienced VLSI RTL Designer to join a fast-growing, venture-backed semiconductor innovator developing next-generation programmable coherent DSP (Digital Signal Processing) solutions for AI infrastructure and cloud connectivity. The ideal candidate will contribute to designing high-performance communication systems from concept to silicon, collaborating with algorithm, verification, DFT, and physical design teams to deliver world-class semiconductor solutions. Key Responsibilities
Collaborate with Algorithm and Architecture teams to translate high-level requirements into efficient hardware implementations. Design and implement RTL for complex digital blocks using Verilog/SystemVerilog/VHDL. Participate in all design stages, including micro-architecture definition, synthesis, and timing analysis. Work with Verification teams to develop testbenches, debug issues, and achieve functional coverage closure. Partner with DFT engineers to ensure designs support scan insertion, ATPG, and BIST. Coordinate with Physical Design teams for floorplanning, timing closure, and routing optimization. Perform post-silicon or pre-silicon debug and analyze waveforms, assertions, and timing reports. Optimize for area, power, and performance (PPA) through iterative design improvements. Maintain accurate documentation for design specifications, interfaces, and design reviews. Contribute to IP/SoC integration and system-level interface verification. Stay up-to-date with industry trends, EDA tools, and advanced verification methodologies. Must-Have Qualifications
Minimum 5 years of experience as an ASIC/VLSI Digital Design Engineer. Strong RTL coding proficiency in Verilog/SystemVerilog/VHDL. Hands-on experience with synthesis, timing analysis, and simulation environments. Sound understanding of DFT concepts – scan insertion, ATPG, and BIST. Proven ability to translate algorithmic concepts into optimized RTL. Solid knowledge of digital design fundamentals and ASIC development flow. Excellent collaboration and communication skills with cross-functional teams. On-site availability in Austin, TX (5 days per week). Nice-to-Have Qualifications
Experience with Optical Communication Systems and Ethernet (100G and above). Background in DSP-oriented designs or high-speed serial interfaces. Experience in IP/SoC integration and system-level debugging. Scripting proficiency in Python, Perl, or TCL. Strong interpersonal skills, self-starter attitude, and entrepreneurial mindset. BS/MS in Electrical or Computer Engineering from a top university. Perks & Benefits
Competitive salary with meaningful equity participation. Full Medical & Dental coverage. Opportunity to work on next-generation semiconductor technology powering AI and cloud infrastructure. Open to H1-B sponsorship. Dynamic startup culture with top-tier venture backing. Exposure to advanced EDA tools, architectures, and silicon bring-up activities.
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Seeking an experienced VLSI RTL Designer to join a fast-growing, venture-backed semiconductor innovator developing next-generation programmable coherent DSP (Digital Signal Processing) solutions for AI infrastructure and cloud connectivity. The ideal candidate will contribute to designing high-performance communication systems from concept to silicon, collaborating with algorithm, verification, DFT, and physical design teams to deliver world-class semiconductor solutions. Key Responsibilities
Collaborate with Algorithm and Architecture teams to translate high-level requirements into efficient hardware implementations. Design and implement RTL for complex digital blocks using Verilog/SystemVerilog/VHDL. Participate in all design stages, including micro-architecture definition, synthesis, and timing analysis. Work with Verification teams to develop testbenches, debug issues, and achieve functional coverage closure. Partner with DFT engineers to ensure designs support scan insertion, ATPG, and BIST. Coordinate with Physical Design teams for floorplanning, timing closure, and routing optimization. Perform post-silicon or pre-silicon debug and analyze waveforms, assertions, and timing reports. Optimize for area, power, and performance (PPA) through iterative design improvements. Maintain accurate documentation for design specifications, interfaces, and design reviews. Contribute to IP/SoC integration and system-level interface verification. Stay up-to-date with industry trends, EDA tools, and advanced verification methodologies. Must-Have Qualifications
Minimum 5 years of experience as an ASIC/VLSI Digital Design Engineer. Strong RTL coding proficiency in Verilog/SystemVerilog/VHDL. Hands-on experience with synthesis, timing analysis, and simulation environments. Sound understanding of DFT concepts – scan insertion, ATPG, and BIST. Proven ability to translate algorithmic concepts into optimized RTL. Solid knowledge of digital design fundamentals and ASIC development flow. Excellent collaboration and communication skills with cross-functional teams. On-site availability in Austin, TX (5 days per week). Nice-to-Have Qualifications
Experience with Optical Communication Systems and Ethernet (100G and above). Background in DSP-oriented designs or high-speed serial interfaces. Experience in IP/SoC integration and system-level debugging. Scripting proficiency in Python, Perl, or TCL. Strong interpersonal skills, self-starter attitude, and entrepreneurial mindset. BS/MS in Electrical or Computer Engineering from a top university. Perks & Benefits
Competitive salary with meaningful equity participation. Full Medical & Dental coverage. Opportunity to work on next-generation semiconductor technology powering AI and cloud infrastructure. Open to H1-B sponsorship. Dynamic startup culture with top-tier venture backing. Exposure to advanced EDA tools, architectures, and silicon bring-up activities.
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