NVIDIA
Senior Physical Verification Engineer, VLSI Implementation
NVIDIA, Phoenix, Arizona, United States
Senior Physical Verification Engineer, VLSI Implementation
We are currently looking for a Sr VLSI Physical Verification Methodology Engineer to support and debug physical implementation of GPU and SOC reticle-sized chips, coordinating with the PNR team to achieve SOL tape‑out. This role involves determining physical verification methodologies to improve workflow efficiency, integrating new checks into automated systems, and developing physical verification flows for emerging technologies such as DRC, LVS, and Antenna.
What You'll Be Doing
Responsible for support and debug of physical implementation GPU and SOC reticle‑sized chips, coordinating with the PNR team to achieve SOL tape‑out – including feedback recognition and correlation.
Determining physical verification methodologies to improve workflow efficiency and timely issue detection. Integrate new workflows and checks into larger workflow automation systems.
Participate in developing physical verification flows for new technologies - DRC, LVS, Antenna flows - improving automation and expert workflows.
TSMC A16 rules and tape‑out experience is preferred.
What We Need To See
BS/MS in Electrical Engineering or related field (or equivalent experience)
Minimum 4+ years of physical implementation experience with 4+ years in physical verification build and debug (can run concurrently).
Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.
Strong knowledge and experience with Physical Verification debug of shorts/compare results across DRC/LVS/Antenna related issues in both PV signoff tools as well as EDA implementation tools (ICC2/Innovus/other)
Direct experience with ICV and Calibre runsets for physical verification of DRC/LVS/Antenna.
Good scripting skills in Python/Perl or other related automation languages.
Ways To Stand Out From The Crowd
Exposure to Virtuoso or ICWeb platforms, AI application to PV analysis or workflows, workflow automation experience.
Proficient in writing DRC/LVS rules, including advanced checks tailored to specific design requirements for ICV and CALIBRE tools.
Understanding of AI Chat and/or Agentive systems applied in the PV domain.
NVIDIA is widely considered to be one of the technology world’s most desirable employers, and due to outstanding success, our teams are rapidly growing.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 8, 2025. NVIDIA is committed to fostering a diverse work environment and proud to be an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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What You'll Be Doing
Responsible for support and debug of physical implementation GPU and SOC reticle‑sized chips, coordinating with the PNR team to achieve SOL tape‑out – including feedback recognition and correlation.
Determining physical verification methodologies to improve workflow efficiency and timely issue detection. Integrate new workflows and checks into larger workflow automation systems.
Participate in developing physical verification flows for new technologies - DRC, LVS, Antenna flows - improving automation and expert workflows.
TSMC A16 rules and tape‑out experience is preferred.
What We Need To See
BS/MS in Electrical Engineering or related field (or equivalent experience)
Minimum 4+ years of physical implementation experience with 4+ years in physical verification build and debug (can run concurrently).
Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.
Strong knowledge and experience with Physical Verification debug of shorts/compare results across DRC/LVS/Antenna related issues in both PV signoff tools as well as EDA implementation tools (ICC2/Innovus/other)
Direct experience with ICV and Calibre runsets for physical verification of DRC/LVS/Antenna.
Good scripting skills in Python/Perl or other related automation languages.
Ways To Stand Out From The Crowd
Exposure to Virtuoso or ICWeb platforms, AI application to PV analysis or workflows, workflow automation experience.
Proficient in writing DRC/LVS rules, including advanced checks tailored to specific design requirements for ICV and CALIBRE tools.
Understanding of AI Chat and/or Agentive systems applied in the PV domain.
NVIDIA is widely considered to be one of the technology world’s most desirable employers, and due to outstanding success, our teams are rapidly growing.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 8, 2025. NVIDIA is committed to fostering a diverse work environment and proud to be an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
#J-18808-Ljbffr