Altera
Senior SOC Physical Design/Power Analysis/RDL Engineer
Altera, San Jose, California, United States, 95199
Senior SOC Physical Design/Power Analysis/RDL Engineer
Accelerating innovators – Altera provides leadership programmable solutions that are easy to use and deploy across the cloud to the edge, enabling limitless possibilities for AI. Our portfolio includes FPGAs, SoCs, CPLDs, IP, development tools, system‑on‑modules, SmartNICs and IPUs, offering flexibility to accelerate innovation. Altera seeks a Sr. SoC Physical Design/Power Analysis/RDL Engineer to join our SoC Physical Design Team. Responsibilities
Perform Physical Design Implementation and Power Integrity Static and Dynamic Analysis for SoC block level and subsystem level. Offer expertise in BUMP/RDL/MIMCAP planning and implementation. Conduct all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Execute verification and signoff including formal equivalence verification, STA, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Apply design optimization knowledge to improve product‑level parameters such as power, frequency, and area, and participate in developing and improving physical design methodologies and flow automation. Qualifications
Bachelor's degree in computer engineering, electronic engineering or related field. 5+ years of relevant experience including multiple tape‑out at deep submicron process nodes, extensive knowledge of physical design flow and signoff flow (STA, LEC, ERC, DRC), and scripting with Perl, TCL, Python. Experience with VHDL/Verilog hardware description languages. Mentoring experience, strong initiative, analytical/problem‑solving skills, team‑working skills, and ability to multitask in a diverse team environment. Preferred Requirements
7+ years of experience with physical design implementation and static/dynamic power analysis expertise, BUMP/RDL/MIMCAP experience, low‑power design tools and methodologies.
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Accelerating innovators – Altera provides leadership programmable solutions that are easy to use and deploy across the cloud to the edge, enabling limitless possibilities for AI. Our portfolio includes FPGAs, SoCs, CPLDs, IP, development tools, system‑on‑modules, SmartNICs and IPUs, offering flexibility to accelerate innovation. Altera seeks a Sr. SoC Physical Design/Power Analysis/RDL Engineer to join our SoC Physical Design Team. Responsibilities
Perform Physical Design Implementation and Power Integrity Static and Dynamic Analysis for SoC block level and subsystem level. Offer expertise in BUMP/RDL/MIMCAP planning and implementation. Conduct all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Execute verification and signoff including formal equivalence verification, STA, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Apply design optimization knowledge to improve product‑level parameters such as power, frequency, and area, and participate in developing and improving physical design methodologies and flow automation. Qualifications
Bachelor's degree in computer engineering, electronic engineering or related field. 5+ years of relevant experience including multiple tape‑out at deep submicron process nodes, extensive knowledge of physical design flow and signoff flow (STA, LEC, ERC, DRC), and scripting with Perl, TCL, Python. Experience with VHDL/Verilog hardware description languages. Mentoring experience, strong initiative, analytical/problem‑solving skills, team‑working skills, and ability to multitask in a diverse team environment. Preferred Requirements
7+ years of experience with physical design implementation and static/dynamic power analysis expertise, BUMP/RDL/MIMCAP experience, low‑power design tools and methodologies.
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