PDDN Inc.
Role:
Analog Layout Design Engineer Location:
Santa Clara, CA Type:
Contract Interview:
Phone/Skype
We're hiring talented professionals for high-performance analog layout design on advanced CMOS nodes (40nm to 3nm). Must have strong experience in SERDES, PLL, DDR PHYs, and verification tools (LVS, DRC, ERC). Expertise required in
Synopsys ,
Cadence ,
Mentor Graphics ,
TSMC nodes , and
Python . Open to C2C (Genuine H1B with i94 travel history) W2 options available for Green Card holders and US citizens only #AnalogLayout #CMOS #SERDES #PLL #Cadence #MentorGraphics #Python #TSMC #AMSdesign #PhysicalDesign #C2CHiring Additional Information
All your information will be kept confidential according to EEO guidelines.
#J-18808-Ljbffr
Analog Layout Design Engineer Location:
Santa Clara, CA Type:
Contract Interview:
Phone/Skype
We're hiring talented professionals for high-performance analog layout design on advanced CMOS nodes (40nm to 3nm). Must have strong experience in SERDES, PLL, DDR PHYs, and verification tools (LVS, DRC, ERC). Expertise required in
Synopsys ,
Cadence ,
Mentor Graphics ,
TSMC nodes , and
Python . Open to C2C (Genuine H1B with i94 travel history) W2 options available for Green Card holders and US citizens only #AnalogLayout #CMOS #SERDES #PLL #Cadence #MentorGraphics #Python #TSMC #AMSdesign #PhysicalDesign #C2CHiring Additional Information
All your information will be kept confidential according to EEO guidelines.
#J-18808-Ljbffr