AMD
What You Do
At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers to PCs, gaming, and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity, and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.
Role Lead Design Verification Engineer – Networking Chip (Senior)
Responsibilities
Ownership of verification strategy for one or more major IP blocks or subsystems within a complex networking ASIC.
Architect and implement testbenches in UVM/SystemVerilog, ensuring maximum coverage and quality.
Develop and maintain test plans, coverage models, and scoreboards to ensure comprehensive verification of all design features.
Lead and mentor a team of DV engineers—drive reviews, define milestones, and ensure high‑quality deliverables.
Collaborate closely with design, architecture, and software teams to define verification requirements and debug issues across the full chip.
Develop and maintain automation and regression infrastructure, including CI/CD integration.
Drive coverage closure and signoff for IP and SOC‑level verification.
Contribute to methodology improvements, verification IP reuse, and best practices across the DV organization.
Work cross‑functionally with IP/domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements.
Support Post‑Si teams for product performance, power, and functional issue debug/resolution.
Preferred Experience
Proven line management experience, including hiring, mentoring, and performance management of DV engineers.
Demonstrated ability to build and lead high‑performing verification teams, setting goals and driving execution across projects.
Experience with chip‑level verification for networking ASICs, switches, or routers.
Familiarity with traffic generators, packet‑level verification, and network protocol stacks.
Knowledge of SystemC, C testbenches, or hardware/software co‑verification.
Exposure to emulation or FPGA prototyping environments (e.g., Palladium, Veloce).
Prior experience leading cross‑site or multi‑IP verification efforts.
Strong communication, collaboration, and leadership skills with the ability to influence technical direction across disciplines.
Academic Credentials
Bachelor’s or Master’s degree in a related discipline preferred.
Location Santa Clara, CA
Pay Range Base: $221,360.00 per year – $332,040.00 per year
EEO Statement AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
#J-18808-Ljbffr
Role Lead Design Verification Engineer – Networking Chip (Senior)
Responsibilities
Ownership of verification strategy for one or more major IP blocks or subsystems within a complex networking ASIC.
Architect and implement testbenches in UVM/SystemVerilog, ensuring maximum coverage and quality.
Develop and maintain test plans, coverage models, and scoreboards to ensure comprehensive verification of all design features.
Lead and mentor a team of DV engineers—drive reviews, define milestones, and ensure high‑quality deliverables.
Collaborate closely with design, architecture, and software teams to define verification requirements and debug issues across the full chip.
Develop and maintain automation and regression infrastructure, including CI/CD integration.
Drive coverage closure and signoff for IP and SOC‑level verification.
Contribute to methodology improvements, verification IP reuse, and best practices across the DV organization.
Work cross‑functionally with IP/domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements.
Support Post‑Si teams for product performance, power, and functional issue debug/resolution.
Preferred Experience
Proven line management experience, including hiring, mentoring, and performance management of DV engineers.
Demonstrated ability to build and lead high‑performing verification teams, setting goals and driving execution across projects.
Experience with chip‑level verification for networking ASICs, switches, or routers.
Familiarity with traffic generators, packet‑level verification, and network protocol stacks.
Knowledge of SystemC, C testbenches, or hardware/software co‑verification.
Exposure to emulation or FPGA prototyping environments (e.g., Palladium, Veloce).
Prior experience leading cross‑site or multi‑IP verification efforts.
Strong communication, collaboration, and leadership skills with the ability to influence technical direction across disciplines.
Academic Credentials
Bachelor’s or Master’s degree in a related discipline preferred.
Location Santa Clara, CA
Pay Range Base: $221,360.00 per year – $332,040.00 per year
EEO Statement AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
#J-18808-Ljbffr