Silvus Technologies
Senior FPGA / RTL Design Engineer - Signal Processing
Silvus Technologies, Los Angeles, California, United States, 90079
Overview
Senior FPGA / RTL Design Engineer - Signal Processing at Silvus Technologies. Role reports to the Director of FPGA Engineering. The successful candidate will participate in all aspects of the research and development process, from concept to field deployment, and will implement novel signal processing algorithms for Silvus\' MIMO wireless networking products. This position is based at Silvus headquarters in West Los Angeles, CA and follows a hybrid schedule with a minimum of 3 days onsite per week (Mondays, Wednesdays, and Thursdays). Responsibilities
Digital design architecting for wireless communication projects. Fixed point design of signal processing blocks in collaboration with systems engineers. RTL coding, simulation, and test bench development. FPGA synthesis and timing closure. Hardware verification and troubleshooting; familiarity with logic analyzers. Provide support to the RF and Software Engineering teams. Required Qualifications
Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields. Minimum 6 years of demonstrated experience in FPGA design; 4 years with a Master\'s degree; 2 years with a doctoral degree. Demonstrated experience with fixed point binary arithmetic and digital signal processing designs. Proven expertise with multiple clock-domain, high-utilization FPGA designs. Experience with Xilinx FPGAs, SoCs, and the Vivado IDE. Must be a U.S. Person (U.S. Citizen or Permanent Resident) due to clients under U.S. federal contracts. All employment is contingent upon successful clearance of a background check. Preferred Knowledge, Skills, And Abilities
Master of Science degree in Electrical Engineering (MSEE). Experience using MATLAB. Experience with communication systems on FPGA or ASIC designs. Working Conditions
Office environment. Occasional exposure to heat, cold, and allergens during field tests or demonstrations. Physical requirements: lift up to 20 lbs; bending, reaching, kneeling or squatting to access equipment; walking/moving in labs. Compensation
The pay range is NOT a guarantee. It is based on market data and will vary based on experience and qualifications. California pay range: $125,000 - $195,000 USD. Note: As a U.S. Federal Contractor, all candidates for employment must be a U.S. Person. Stricter U.S. Citizen requirements may apply for some roles. All employment is contingent upon successful background check. Equal Opportunity
Silvus is an equal-opportunity employer. We do not discriminate on the basis of race, color, age, religion, national origin, sex, sexual orientation, gender identity, marital status, disability, protected veteran status, genetic information, or any other factor protected by applicable laws. Reasonable accommodations are provided to applicants with disabilities upon request. Silvus does not accept unsolicited resumes from recruiters or third-party agencies without a prior written agreement.
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Senior FPGA / RTL Design Engineer - Signal Processing at Silvus Technologies. Role reports to the Director of FPGA Engineering. The successful candidate will participate in all aspects of the research and development process, from concept to field deployment, and will implement novel signal processing algorithms for Silvus\' MIMO wireless networking products. This position is based at Silvus headquarters in West Los Angeles, CA and follows a hybrid schedule with a minimum of 3 days onsite per week (Mondays, Wednesdays, and Thursdays). Responsibilities
Digital design architecting for wireless communication projects. Fixed point design of signal processing blocks in collaboration with systems engineers. RTL coding, simulation, and test bench development. FPGA synthesis and timing closure. Hardware verification and troubleshooting; familiarity with logic analyzers. Provide support to the RF and Software Engineering teams. Required Qualifications
Bachelor of Science degree in Electrical Engineering, Computer Science, or related fields. Minimum 6 years of demonstrated experience in FPGA design; 4 years with a Master\'s degree; 2 years with a doctoral degree. Demonstrated experience with fixed point binary arithmetic and digital signal processing designs. Proven expertise with multiple clock-domain, high-utilization FPGA designs. Experience with Xilinx FPGAs, SoCs, and the Vivado IDE. Must be a U.S. Person (U.S. Citizen or Permanent Resident) due to clients under U.S. federal contracts. All employment is contingent upon successful clearance of a background check. Preferred Knowledge, Skills, And Abilities
Master of Science degree in Electrical Engineering (MSEE). Experience using MATLAB. Experience with communication systems on FPGA or ASIC designs. Working Conditions
Office environment. Occasional exposure to heat, cold, and allergens during field tests or demonstrations. Physical requirements: lift up to 20 lbs; bending, reaching, kneeling or squatting to access equipment; walking/moving in labs. Compensation
The pay range is NOT a guarantee. It is based on market data and will vary based on experience and qualifications. California pay range: $125,000 - $195,000 USD. Note: As a U.S. Federal Contractor, all candidates for employment must be a U.S. Person. Stricter U.S. Citizen requirements may apply for some roles. All employment is contingent upon successful background check. Equal Opportunity
Silvus is an equal-opportunity employer. We do not discriminate on the basis of race, color, age, religion, national origin, sex, sexual orientation, gender identity, marital status, disability, protected veteran status, genetic information, or any other factor protected by applicable laws. Reasonable accommodations are provided to applicants with disabilities upon request. Silvus does not accept unsolicited resumes from recruiters or third-party agencies without a prior written agreement.
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