Intel
Overview
Do Something Wonderful! Intel puts Silicon in Silicon Valley. We are obsessed with engineering and building a brighter future. Every day, we create world changing technology that enriches the lives of people on earth. If you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Who We Are You will be part of a high performing team specializing in clocking architecture, clock distribution network design, custom clock circuits, clock tree synthesis, and low power design for Intel’s flagship IA cores in the most advanced process nodes. Who You Are Your responsibilities will include but are not limited to: Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to improve current and future CPU microarchitectures, closely collaborating with logic, circuit, architecture, and design automation teams.
Possesses CPU-specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
Works closely with industry EDA vendors to build and enhance tool capabilities to design a high-speed, low-power synthesizable CPU.
Optimizes CPU design to improve product-level parameters such as power, frequency, and area.
Participates in the development and improvement of physical design methodologies and flow automation.
Maintains a good understanding of static timing analysis, clock-related timing parameters, EM, IR, and Place and Route flows.
Demonstrates strong understanding of sub-micron process technology and circuits.
Exhibits excellent written and communication skills.
Works well independently and develops quick engineering solutions for complex problems.
Interfaces effectively with engineers and managers by providing schedule updates.
Shows high problem-solving skills and tolerance for ambiguity.
Prioritizes tasks independently with a focus on quality, discipline, and accurate results for engineering customers.
Contributes and works well in a multi-site team setting.
Qualifications: You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications The ideal candidate must have a Master’s Degree in Electrical Engineering, Computer Engineering or related STEM field with 3+ years of experience including: Backend design and/or integration on leading-edge process nodes
Perl, TCL, or other industry-standard scripting languages
High-frequency clock distribution design and implementation, custom circuits and clock tree synthesis
Preferred Qualifications Experience with computer architecture
Experience with IA-32 assembly and/or Verilog programming
Experience with validation or testing, especially in a silicon design team
Job Type:
Experienced Hire Shift:
Shift 1 Primary Location:
US, Texas, Austin Additional Locations:
US, Oregon, Hillsboro Business group:
The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This group leverages a diverse mix of experts to innovate in computing experiences. Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, ancestry, age, disability, genetic information, military and veteran status, marital status, pregnancy, gender identity, sexual orientation, or any other characteristic protected by local law. Benefits: We offer a total compensation package including competitive pay, stock, bonuses, and benefits programs such as health, retirement, and vacation. For more information about benefits, please refer to the company materials provided with this posting. Salary
range: $153,540.00 – $216,770.00 (dependent on location and experience). Work Model for this Role:
This role will require on-site presence. Job posting details (such as work model, location or time type) are subject to change.
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Do Something Wonderful! Intel puts Silicon in Silicon Valley. We are obsessed with engineering and building a brighter future. Every day, we create world changing technology that enriches the lives of people on earth. If you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Who We Are You will be part of a high performing team specializing in clocking architecture, clock distribution network design, custom clock circuits, clock tree synthesis, and low power design for Intel’s flagship IA cores in the most advanced process nodes. Who You Are Your responsibilities will include but are not limited to: Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to improve current and future CPU microarchitectures, closely collaborating with logic, circuit, architecture, and design automation teams.
Possesses CPU-specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
Works closely with industry EDA vendors to build and enhance tool capabilities to design a high-speed, low-power synthesizable CPU.
Optimizes CPU design to improve product-level parameters such as power, frequency, and area.
Participates in the development and improvement of physical design methodologies and flow automation.
Maintains a good understanding of static timing analysis, clock-related timing parameters, EM, IR, and Place and Route flows.
Demonstrates strong understanding of sub-micron process technology and circuits.
Exhibits excellent written and communication skills.
Works well independently and develops quick engineering solutions for complex problems.
Interfaces effectively with engineers and managers by providing schedule updates.
Shows high problem-solving skills and tolerance for ambiguity.
Prioritizes tasks independently with a focus on quality, discipline, and accurate results for engineering customers.
Contributes and works well in a multi-site team setting.
Qualifications: You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications The ideal candidate must have a Master’s Degree in Electrical Engineering, Computer Engineering or related STEM field with 3+ years of experience including: Backend design and/or integration on leading-edge process nodes
Perl, TCL, or other industry-standard scripting languages
High-frequency clock distribution design and implementation, custom circuits and clock tree synthesis
Preferred Qualifications Experience with computer architecture
Experience with IA-32 assembly and/or Verilog programming
Experience with validation or testing, especially in a silicon design team
Job Type:
Experienced Hire Shift:
Shift 1 Primary Location:
US, Texas, Austin Additional Locations:
US, Oregon, Hillsboro Business group:
The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This group leverages a diverse mix of experts to innovate in computing experiences. Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, ancestry, age, disability, genetic information, military and veteran status, marital status, pregnancy, gender identity, sexual orientation, or any other characteristic protected by local law. Benefits: We offer a total compensation package including competitive pay, stock, bonuses, and benefits programs such as health, retirement, and vacation. For more information about benefits, please refer to the company materials provided with this posting. Salary
range: $153,540.00 – $216,770.00 (dependent on location and experience). Work Model for this Role:
This role will require on-site presence. Job posting details (such as work model, location or time type) are subject to change.
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