Intrepidus Talent Solutions
SeniorPrincipal ASIC Digital Design Engineer
Intrepidus Talent Solutions, Boise, Idaho, United States, 83708
About the Company
Life is short — solve hard problems with great people.
Our client is a rapidly growing technology firm that blends the innovation and agility of a startup with the stability and resources of an established organization. The company develops secure system solutions that protect U.S. military and critical infrastructure through advanced CPU design, custom crypto cores, purpose‑built system‑on‑chip architectures, and hardened operating systems.
Their work directly impacts how national defense and critical systems remain secure in unpredictable environments — and they’re looking for talented engineers who want to solve hard problems that truly matter.
The Opportunity We are seeking an experienced
Senior/Principal
ASIC Digital Design Engineer
to join a high‑impact team focused on developing next‑generation secure hardware solutions. The ideal candidate will bring a mix of deep technical expertise, hands‑on design experience, and a collaborative mindset to deliver cutting‑edge system‑on‑chip solutions for real‑world applications.
Key Responsibilities
Collaborate with engineering leaders to identify core technical challenges and define effective solutions
Develop and define the microarchitecture of new IP to optimize performance, I/O, power, area utilization, recurring cost, and security functions
Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other relevant languages
Integrate complex systems that incorporate both proprietary and third‑party IP
Contribute to the entire design lifecycle—from specification through production
Apply advanced IP to ASIC and FPGA systems in real‑world deployments
Enhance and refine design methodologies and internal processes
Mentor and support other ASIC design engineers
Required Qualifications & Experience
U.S. Citizenship
Proven experience designing and fabricating an ASIC
Ability to obtain a U.S. security clearance
5+ years of experience in FPGA or ASIC product development
Bachelor’s degree (or higher) in Computer Engineering, Electrical Engineering, Computer Science, or related discipline
Deep understanding of digital architectures and design methods (RTL coding, synthesis, place‑and‑route, timing closure, and formal verification)
Strong analytical and problem‑solving skills
Excellent communication skills, written and verbal
High attention to detail and a proactive, hands‑on approach
Demonstrated success working effectively across cross‑functional teams
Preferred Qualifications & Experience
Active or current U.S. Security Clearance (within the past two years)
In‑depth understanding of microprocessor architectures
Working knowledge of applied cryptography and cybersecurity concepts
Experience applying cybersecurity principles to embedded or operational technology systems
Familiarity with SystemVerilog, VHDL, and Test‑Driven Development practices
Location This role can be based in Boise, ID or Baltimore, MD
Why Join This is an opportunity to contribute to mission‑critical technology while enjoying a balanced and rewarding professional experience. The company offers:
Competitive compensation and profit‑sharing
Flexible work schedule
Comprehensive health benefits and insurance
Retirement fund contributions
Generous paid time off
#J-18808-Ljbffr
Their work directly impacts how national defense and critical systems remain secure in unpredictable environments — and they’re looking for talented engineers who want to solve hard problems that truly matter.
The Opportunity We are seeking an experienced
Senior/Principal
ASIC Digital Design Engineer
to join a high‑impact team focused on developing next‑generation secure hardware solutions. The ideal candidate will bring a mix of deep technical expertise, hands‑on design experience, and a collaborative mindset to deliver cutting‑edge system‑on‑chip solutions for real‑world applications.
Key Responsibilities
Collaborate with engineering leaders to identify core technical challenges and define effective solutions
Develop and define the microarchitecture of new IP to optimize performance, I/O, power, area utilization, recurring cost, and security functions
Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other relevant languages
Integrate complex systems that incorporate both proprietary and third‑party IP
Contribute to the entire design lifecycle—from specification through production
Apply advanced IP to ASIC and FPGA systems in real‑world deployments
Enhance and refine design methodologies and internal processes
Mentor and support other ASIC design engineers
Required Qualifications & Experience
U.S. Citizenship
Proven experience designing and fabricating an ASIC
Ability to obtain a U.S. security clearance
5+ years of experience in FPGA or ASIC product development
Bachelor’s degree (or higher) in Computer Engineering, Electrical Engineering, Computer Science, or related discipline
Deep understanding of digital architectures and design methods (RTL coding, synthesis, place‑and‑route, timing closure, and formal verification)
Strong analytical and problem‑solving skills
Excellent communication skills, written and verbal
High attention to detail and a proactive, hands‑on approach
Demonstrated success working effectively across cross‑functional teams
Preferred Qualifications & Experience
Active or current U.S. Security Clearance (within the past two years)
In‑depth understanding of microprocessor architectures
Working knowledge of applied cryptography and cybersecurity concepts
Experience applying cybersecurity principles to embedded or operational technology systems
Familiarity with SystemVerilog, VHDL, and Test‑Driven Development practices
Location This role can be based in Boise, ID or Baltimore, MD
Why Join This is an opportunity to contribute to mission‑critical technology while enjoying a balanced and rewarding professional experience. The company offers:
Competitive compensation and profit‑sharing
Flexible work schedule
Comprehensive health benefits and insurance
Retirement fund contributions
Generous paid time off
#J-18808-Ljbffr