Avalanche Technology
Viewing Position: Design Verification Engineer
Our Engineering team is seeking a Design Verification Engineer to join our onsite team and work closely with our design group. In this role, you will develop UVM-based verification environments, create and execute tests for digital and mixed-signal designs, and drive block- and subsystem-level verification. You’ll collaborate with RTL and mixed-signal engineers, run FastSPICE and RTL simulations using Cadence Xcelium, analyze results, and ensure high-quality verification coverage. This is an exciting opportunity to contribute to cutting‑edge semiconductor projects and grow your expertise in a dynamic, collaborative environment.
Duties and Responsibilities
Develop UVM-based verification environments and testbenches in SystemVerilog.
Own block- and subsystem-level verification for digital and mixed‑signal designs.
Create directed and constrained‑random tests, assertions (SVA), and functional coverage models.
Set up and run FastSPICE-level simulations using industry tools.
Use Cadence Xcelium for Verilog RTL simulation and debug.
Analyze simulation results, debug functional failures, and collaborate closely with RTL and mixed‑signal teams.
Maintain regressions, coverage metrics, and bug tracking.
Preferred
Experience verifying non-volatile memory, memory controllers, or mixed‑signal interfaces.
Exposure to firmware/hardware co‑verification environments.
Familiarity with formal verification flows.
Minimum Qualifications
3+ years of design verification experience with SystemVerilog and UVM.
Hands‑on experience with Cadence Xcelium or similar RTL simulators.
>Experience with FastSPICE simulation tools (e.g., AFS, Spectre XPS, or similar). Strong understanding of digital logic, FSMs, SoC interconnects (AXI, AHB).
Scripting proficiency in Python, Perl, or Tcl for test automation and debug support.
Skilled in waveform debugging (SimVision, DVE, etc.)
Education
S. or M.S. in Electrical or Computer Engineering.
About Avalanche Technology Avalanche Technology is a leading developer of Magnetic Random Access Memory (MRAM) solutions. Our non‑volatile products are trusted in mission‑critical applications where reliability under extreme conditions is paramount. We are headquartered in Fremont, CA and operate with a close‑knit, high‑impact engineering and operations team.
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Our Engineering team is seeking a Design Verification Engineer to join our onsite team and work closely with our design group. In this role, you will develop UVM-based verification environments, create and execute tests for digital and mixed-signal designs, and drive block- and subsystem-level verification. You’ll collaborate with RTL and mixed-signal engineers, run FastSPICE and RTL simulations using Cadence Xcelium, analyze results, and ensure high-quality verification coverage. This is an exciting opportunity to contribute to cutting‑edge semiconductor projects and grow your expertise in a dynamic, collaborative environment.
Duties and Responsibilities
Develop UVM-based verification environments and testbenches in SystemVerilog.
Own block- and subsystem-level verification for digital and mixed‑signal designs.
Create directed and constrained‑random tests, assertions (SVA), and functional coverage models.
Set up and run FastSPICE-level simulations using industry tools.
Use Cadence Xcelium for Verilog RTL simulation and debug.
Analyze simulation results, debug functional failures, and collaborate closely with RTL and mixed‑signal teams.
Maintain regressions, coverage metrics, and bug tracking.
Preferred
Experience verifying non-volatile memory, memory controllers, or mixed‑signal interfaces.
Exposure to firmware/hardware co‑verification environments.
Familiarity with formal verification flows.
Minimum Qualifications
3+ years of design verification experience with SystemVerilog and UVM.
Hands‑on experience with Cadence Xcelium or similar RTL simulators.
>Experience with FastSPICE simulation tools (e.g., AFS, Spectre XPS, or similar). Strong understanding of digital logic, FSMs, SoC interconnects (AXI, AHB).
Scripting proficiency in Python, Perl, or Tcl for test automation and debug support.
Skilled in waveform debugging (SimVision, DVE, etc.)
Education
S. or M.S. in Electrical or Computer Engineering.
About Avalanche Technology Avalanche Technology is a leading developer of Magnetic Random Access Memory (MRAM) solutions. Our non‑volatile products are trusted in mission‑critical applications where reliability under extreme conditions is paramount. We are headquartered in Fremont, CA and operate with a close‑knit, high‑impact engineering and operations team.
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