Advanced Technology Search
Package Design Engineer
Advanced Technology Search, San Jose, California, United States, 95199
Our client is seeking an experienced
Package Design Engineer
for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and RF/microwave communications A/D D/A converters (ADC & DAC).
You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 112G and higher, RF/Microwave ADC/DAC, DDR and more. You’ll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and also automate design tasks using Cadence SKILL.
RESPONSIBILITIES
Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest
Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
Schedule, prioritize, & track your work across 2+ projects simultaneously
EDUCATION/EXPERIENCE & REQUIREMENTS
BSEE or similar field and 12+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
MSEE or similar field and 10+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
Knowledge of package-level signal integrity and power integrity, to apply to package designs
Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers
#J-18808-Ljbffr
Package Design Engineer
for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and RF/microwave communications A/D D/A converters (ADC & DAC).
You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 112G and higher, RF/Microwave ADC/DAC, DDR and more. You’ll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and also automate design tasks using Cadence SKILL.
RESPONSIBILITIES
Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest
Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
Schedule, prioritize, & track your work across 2+ projects simultaneously
EDUCATION/EXPERIENCE & REQUIREMENTS
BSEE or similar field and 12+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
MSEE or similar field and 10+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
Knowledge of package-level signal integrity and power integrity, to apply to package designs
Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers
#J-18808-Ljbffr