Broadcom
IP Integration Engineer
Broadcom’s ASIC Product Division (APD) is focused on enabling customers to develop products with a sustainable and substantial competitive advantage. APD does this by delivering best in class technology platforms, easy to integrate bleeding edge intellectual property, and by providing world class customer support. APD’s customers span a wide range of industries developing ASICs for largest and most complex cloud computing AI engines, supercomputers, networking, to low power and most advanced wireless solutions, as some examples.
As an IP Integration Engineer, you will be part of a cross‑functional design team developing die‑to‑die and die‑to‑memory PHY IP used broadly in APD's custom silicon ASIC products. The role involves the development of the physical composition (hardening of the PHY) as well as defining methodologies for integrating these into large complex 2.5D and 3.5D ASICs. This position is located in Fort Collins, CO.
Job Requirements
A Bachelor’s Degree in Electrical or Computer Engineering or equivalent, and 5+ years of related experience; or a Masters degree and 3+ years of related experience
Understanding of design trade‑offs for power, area, and speed in ASIC designs
Understanding of the ASIC design flow including FET design, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC
Basic understanding of modern FET architecture including FinFET and Gate All‑Around (GAA) topologies
Experience with Cadence Innovus or equivalent toolset
Experience in reading timing reports from static timing tools such as Tempus or Primetime
Strong verbal and written communication
Team player that can easily work with different personalities and skill levels
Ability to multitask and manage multiple technical issues in parallel
Well organized, methodical, and detail oriented
Must develop, accurately track, and meet commitments to product or engineering development schedules
Desired
Experience with the Cadence Virtuoso design environment
Experience or coursework with RTL languages (i.e., SystemVerilog, Verilog, VHDL)
Experience scripting in Skill, TCL, Ruby, Bash, Perl, Python, etc.
Familiar with timing reports and strategies for fixing violations
Experience or familiarity with Ansys Redhawk
Working knowledge with AI tools such as Chat GPT, Gemini, and/or Cursor
Typical Duties
Develop a detailed understanding of Broadcom's die‑to‑die PHYs
Work with multiple cross‑functional teams—analog design, digital design, physical composition, DFT, timing, and customers—to build PHYs
Work with physical composition teams and interposer design teams
Work with analog and physical composition teams to optimize the size and power delivery to high‑IO density PHYs
Analyze power integrity (droop, EM, etc.) in various use cases and workloads
Develop and write PHY integration documentation for ASIC composition teams
Develop a checklist of tasks for integration of PHY IP into ASICs
Work with IP build teams to complete quality cross‑checks to ensure the quality of the PHYs
Help support customer and ASIC PHY integration questions
Compensation and Benefits The annual base salary range for this position is $91,000 - $146,000. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Equal Opportunity Employer Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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As an IP Integration Engineer, you will be part of a cross‑functional design team developing die‑to‑die and die‑to‑memory PHY IP used broadly in APD's custom silicon ASIC products. The role involves the development of the physical composition (hardening of the PHY) as well as defining methodologies for integrating these into large complex 2.5D and 3.5D ASICs. This position is located in Fort Collins, CO.
Job Requirements
A Bachelor’s Degree in Electrical or Computer Engineering or equivalent, and 5+ years of related experience; or a Masters degree and 3+ years of related experience
Understanding of design trade‑offs for power, area, and speed in ASIC designs
Understanding of the ASIC design flow including FET design, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC
Basic understanding of modern FET architecture including FinFET and Gate All‑Around (GAA) topologies
Experience with Cadence Innovus or equivalent toolset
Experience in reading timing reports from static timing tools such as Tempus or Primetime
Strong verbal and written communication
Team player that can easily work with different personalities and skill levels
Ability to multitask and manage multiple technical issues in parallel
Well organized, methodical, and detail oriented
Must develop, accurately track, and meet commitments to product or engineering development schedules
Desired
Experience with the Cadence Virtuoso design environment
Experience or coursework with RTL languages (i.e., SystemVerilog, Verilog, VHDL)
Experience scripting in Skill, TCL, Ruby, Bash, Perl, Python, etc.
Familiar with timing reports and strategies for fixing violations
Experience or familiarity with Ansys Redhawk
Working knowledge with AI tools such as Chat GPT, Gemini, and/or Cursor
Typical Duties
Develop a detailed understanding of Broadcom's die‑to‑die PHYs
Work with multiple cross‑functional teams—analog design, digital design, physical composition, DFT, timing, and customers—to build PHYs
Work with physical composition teams and interposer design teams
Work with analog and physical composition teams to optimize the size and power delivery to high‑IO density PHYs
Analyze power integrity (droop, EM, etc.) in various use cases and workloads
Develop and write PHY integration documentation for ASIC composition teams
Develop a checklist of tasks for integration of PHY IP into ASICs
Work with IP build teams to complete quality cross‑checks to ensure the quality of the PHYs
Help support customer and ASIC PHY integration questions
Compensation and Benefits The annual base salary range for this position is $91,000 - $146,000. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Equal Opportunity Employer Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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