Senior ASIC PD Engineer — Cache Coherence (Equity)

A leading technology company in California is seeking an experienced Senior ASIC Physical Design Engineer to be responsible for the physical design of CPU on-chip interconnect networks and caches. The ideal candidate holds a Master’s Degree and has over 5 years of experience in semiconductor design. This position offers a competitive salary range of $136,000 - $212,750 based on experience, with eligibility for equity and benefits in a diverse workplace. #J-18808-Ljbffr