Akkodis
This range is provided by Akkodis. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range $70.00/hr - $100.00/hr
Akkodis is seeking several full time
ASIC Layout Design Engineer's
with our dedicated onsite team in the Boulder, CO area for a hybrid role (3x/week in office required) with option for direct hire at a later point of time. Candidates shall possess greater than 6 years of professional experience in RF/Analog/Mixed Signal layout design.
Starting Pay Range: $75 to $100+/hr (Pay commensurate based on experience and education levels).
Responsibilities
Layout of cells, blocks, and chips in CMOS, BiCMOS, and Bipolar processes
Chip-level assembly, verification, and debugging
Planning and managing layout teams, including contractors and teammates
Layout tool development and training
Troubleshooting layout software and PDKs
Driving top-down abstraction and black-box methodology
Qualifications
Minimum 6 years of experience in RF/Analog/Mixed Signal layout design.
Proficient in broadband RF/high-speed layout, sensitive RF analog matching, and parasitic minimization.
Experience with PDKs and multiple foundry processes.
Skilled in efficient chip, block, and cell floor planning and signal path optimization.
Strong understanding of: Electromigration, Well-proximity and length-of-diffusion effects, Common-centroid matching, Differential pairs, Current mirrors.
Comfortable with arrays, mirrored, and quadrature layouts.
Expertise in RF, analog, and digital routing, physical verification, and database management.
Familiarity with layout of: DAC/ADC, Broadband amplifiers, VGAs, Regulators, VCOs, PLLs, dividers, Samplers, Bandgaps, Charge pumps, IO/ESD structures.
Strong understanding of RF, analog, digital, and mixed-signal fundamentals.
Excellent communication and interpersonal skills
Strong teamwork and leadership capabilities
Ability to mentor and collaborate across teams
CAD Tools
Cadence Virtuoso Schematic L, Layout L and XL.
Physical Verification & Extraction: Cadence Assura, PVS, Pegasus, Mentor Graphics Calibre.
Design Management: SVN, SOS, Synchronicity, IC Manage (or similar).
Programming/Scripting
Python, Ruby, or Shell scripting is helpful, though not required.
Bonus
Knowledge of Cadence Allegro PCB Design.
Employment Details
Seniority level: Mid-Senior level
Employment type: Contract
Job function: Engineering and Quality Assurance
Industries: Appliances, Electrical, and Electronics Manufacturing
Benefits
Medical insurance
Dental insurance
Vision insurance
Life insurance
Short-term disability
Additional voluntary benefits
EAP program
Commuter benefits
401K plan
Paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law
Holiday pay where applicable
Equal Opportunity Employer/Veterans/Disabled
If you are interested in our
ASIC Layout Design Engineer
role, please click EASY APPLY. For other opportunities available at Akkodis go to www.akkodis.com.
#J-18808-Ljbffr
Base pay range $70.00/hr - $100.00/hr
Akkodis is seeking several full time
ASIC Layout Design Engineer's
with our dedicated onsite team in the Boulder, CO area for a hybrid role (3x/week in office required) with option for direct hire at a later point of time. Candidates shall possess greater than 6 years of professional experience in RF/Analog/Mixed Signal layout design.
Starting Pay Range: $75 to $100+/hr (Pay commensurate based on experience and education levels).
Responsibilities
Layout of cells, blocks, and chips in CMOS, BiCMOS, and Bipolar processes
Chip-level assembly, verification, and debugging
Planning and managing layout teams, including contractors and teammates
Layout tool development and training
Troubleshooting layout software and PDKs
Driving top-down abstraction and black-box methodology
Qualifications
Minimum 6 years of experience in RF/Analog/Mixed Signal layout design.
Proficient in broadband RF/high-speed layout, sensitive RF analog matching, and parasitic minimization.
Experience with PDKs and multiple foundry processes.
Skilled in efficient chip, block, and cell floor planning and signal path optimization.
Strong understanding of: Electromigration, Well-proximity and length-of-diffusion effects, Common-centroid matching, Differential pairs, Current mirrors.
Comfortable with arrays, mirrored, and quadrature layouts.
Expertise in RF, analog, and digital routing, physical verification, and database management.
Familiarity with layout of: DAC/ADC, Broadband amplifiers, VGAs, Regulators, VCOs, PLLs, dividers, Samplers, Bandgaps, Charge pumps, IO/ESD structures.
Strong understanding of RF, analog, digital, and mixed-signal fundamentals.
Excellent communication and interpersonal skills
Strong teamwork and leadership capabilities
Ability to mentor and collaborate across teams
CAD Tools
Cadence Virtuoso Schematic L, Layout L and XL.
Physical Verification & Extraction: Cadence Assura, PVS, Pegasus, Mentor Graphics Calibre.
Design Management: SVN, SOS, Synchronicity, IC Manage (or similar).
Programming/Scripting
Python, Ruby, or Shell scripting is helpful, though not required.
Bonus
Knowledge of Cadence Allegro PCB Design.
Employment Details
Seniority level: Mid-Senior level
Employment type: Contract
Job function: Engineering and Quality Assurance
Industries: Appliances, Electrical, and Electronics Manufacturing
Benefits
Medical insurance
Dental insurance
Vision insurance
Life insurance
Short-term disability
Additional voluntary benefits
EAP program
Commuter benefits
401K plan
Paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law
Holiday pay where applicable
Equal Opportunity Employer/Veterans/Disabled
If you are interested in our
ASIC Layout Design Engineer
role, please click EASY APPLY. For other opportunities available at Akkodis go to www.akkodis.com.
#J-18808-Ljbffr