Senior ASIC PD Engineer: Cache Coherent Interconnects

A leading technology company in Austin is seeking a Senior ASIC Physical Design Engineer to join their Cache Coherent Interconnects team. This role involves physical design responsibilities, ensuring performance, timing, and area goals are met, and defining architectures for next-generation interconnects. The ideal candidate will have 5+ years of relevant experience, a master’s degree in a related field, and strong skills in physical design tools. The position offers a competitive salary and promotes a diverse work environment. #J-18808-Ljbffr