Apple Inc.
SoC Physical Design Engineer, STA/Timing
Apple Inc., Sunnyvale, California, United States, 94087
SoC Physical Design Engineer, STA/Timing
Join Apple as a SoC Physical Design Engineer specializing in STA/Timing. In this role, you will be responsible for the physical implementation of design partitions for complex SOCs using advanced process technology. Responsibilities
Collaborate with design teams to understand constraints and improve timing through logic modifications. Work with the Physical Design team to identify issues and share best practices. Create timing ECOs for project tapeouts. Develop and maintain scripts and methodologies for analysis and runs. Document processes and contribute to guidelines and specifications. Perform deep timing path analysis to identify key issues. Implement timing infrastructure. Minimum Qualifications
Bachelor's degree with 3+ years of relevant industry experience. Experience with large design STA and timing closure. Proficiency in Perl and TCL programming. Preferred Qualifications
Hands-on experience in STA. Knowledge of timing in high-performance SoC designs in sub-micron technologies. Understanding of noise, crosstalk, and OCV effects. Experience with circuit modeling, including SPICE. Familiarity with ECO techniques. Strong communication skills to describe issues clearly and follow through to completion.
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Join Apple as a SoC Physical Design Engineer specializing in STA/Timing. In this role, you will be responsible for the physical implementation of design partitions for complex SOCs using advanced process technology. Responsibilities
Collaborate with design teams to understand constraints and improve timing through logic modifications. Work with the Physical Design team to identify issues and share best practices. Create timing ECOs for project tapeouts. Develop and maintain scripts and methodologies for analysis and runs. Document processes and contribute to guidelines and specifications. Perform deep timing path analysis to identify key issues. Implement timing infrastructure. Minimum Qualifications
Bachelor's degree with 3+ years of relevant industry experience. Experience with large design STA and timing closure. Proficiency in Perl and TCL programming. Preferred Qualifications
Hands-on experience in STA. Knowledge of timing in high-performance SoC designs in sub-micron technologies. Understanding of noise, crosstalk, and OCV effects. Experience with circuit modeling, including SPICE. Familiarity with ECO techniques. Strong communication skills to describe issues clearly and follow through to completion.
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