SPACE EXPLORATION TECHNOLOGIES CORP
Design Verification Engineer (Silicon Engineering)
SPACE EXPLORATION TECHNOLOGIES CORP, Redmond, Washington, United States, 98052
Design Verification Engineer (Silicon Engineering)
Redmond, WA — SpaceX is developing technologies to make humanity explore the stars, including Starlink, the world’s most advanced broadband internet system. We design, build, test, and operate all parts of Starlink’s system and are looking for engineers to help maximize its global impact.
We seek a motivated, proactive engineer with strong cross‑disciplinary teamwork skills. In this role you will develop cutting‑edge ASICs for space and ground infrastructure to expand the performance and capabilities of the Starlink network.
Responsibilities
Lead digital ASIC verification at block and system level.
Write and review test plans; develop test harnesses and sequences.
Develop SystemVerilog testbench infrastructure (UVM and non‑UVM) for DSP blocks.
Execute test plans, run regressions, and close on code and functional coverage.
Automate test case generation using Python and MATLAB scripts.
Contribute to pre‑silicon verification, chip bring‑up, and post‑silicon validation.
Be a hands‑on self‑starter capable of fully verifying complex digital designs.
Basic Qualifications
Bachelor’s degree in Electrical Engineering, Computer Science, or Computer Engineering.
At least 2 years of experience in design verification and test bench development.
Preferred Skills & Experience
Advanced degree in Electrical Engineering or Computer Engineering.
Experience with UVM verification methodology.
Strong object‑oriented programming knowledge.
Excellent problem‑solving and coding skills.
Experience with constrained random verification.
Expertise in developing test plans, coverage models, and result analysis.
Proficiency with scripting languages such as Python for automation.
Experience in RTL design, chip bring‑up, and post‑silicon validation.
Ability to work in a dynamic environment with changing requirements.
Additional Requirements
Willingness to work extended hours and weekends as needed.
Compensation & Benefits Pay range: Design Verification Engineer/Level I: $122,500 – $145,000 per year Design Verification Engineer/Level II: $140,000 – $170,000 per year
Additional benefits include company stock and options, discretionary bonuses, employee stock purchase plan, medical/vision/dental coverage, 401(k) plan, short‑ and long‑term disability insurance, life insurance, paid parental leave, paid vacation (3 weeks), and 10 or more paid holidays per year.
Equal Opportunity Employer SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants requiring reasonable accommodation or interested in the EEO compliance questionnaire should contact EEOCCompliance@spacex.com.
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We seek a motivated, proactive engineer with strong cross‑disciplinary teamwork skills. In this role you will develop cutting‑edge ASICs for space and ground infrastructure to expand the performance and capabilities of the Starlink network.
Responsibilities
Lead digital ASIC verification at block and system level.
Write and review test plans; develop test harnesses and sequences.
Develop SystemVerilog testbench infrastructure (UVM and non‑UVM) for DSP blocks.
Execute test plans, run regressions, and close on code and functional coverage.
Automate test case generation using Python and MATLAB scripts.
Contribute to pre‑silicon verification, chip bring‑up, and post‑silicon validation.
Be a hands‑on self‑starter capable of fully verifying complex digital designs.
Basic Qualifications
Bachelor’s degree in Electrical Engineering, Computer Science, or Computer Engineering.
At least 2 years of experience in design verification and test bench development.
Preferred Skills & Experience
Advanced degree in Electrical Engineering or Computer Engineering.
Experience with UVM verification methodology.
Strong object‑oriented programming knowledge.
Excellent problem‑solving and coding skills.
Experience with constrained random verification.
Expertise in developing test plans, coverage models, and result analysis.
Proficiency with scripting languages such as Python for automation.
Experience in RTL design, chip bring‑up, and post‑silicon validation.
Ability to work in a dynamic environment with changing requirements.
Additional Requirements
Willingness to work extended hours and weekends as needed.
Compensation & Benefits Pay range: Design Verification Engineer/Level I: $122,500 – $145,000 per year Design Verification Engineer/Level II: $140,000 – $170,000 per year
Additional benefits include company stock and options, discretionary bonuses, employee stock purchase plan, medical/vision/dental coverage, 401(k) plan, short‑ and long‑term disability insurance, life insurance, paid parental leave, paid vacation (3 weeks), and 10 or more paid holidays per year.
Equal Opportunity Employer SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants requiring reasonable accommodation or interested in the EEO compliance questionnaire should contact EEOCCompliance@spacex.com.
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