The Association of Technology, Management and Applied Engineering
Senior Staff, Serdes Analog Design Engineer
The Association of Technology, Management and Applied Engineering, San Jose, California, United States, 95199
Position Title
Senior Staff, Serdes Analog Design Engineer
Location Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy.
What you’ll do
Design low‑power and low‑voltage analog and custom digital circuit components using advanced CMOS process technologies.
Translate component design specifications to schematics and build simulation test‑benches to evaluate circuit performance, functionality, power consumption, and reliability.
Supervise layout designers to generate LVS/DRC clean layout and optimize layout to improve power consumption and performance of circuits.
Validate functionality and performance in silicon.
What you bring
Bachelor’s with 15+ years, Master’s with 13+ years or PhDs with 10+ years of experience.
Minimum 2+ years of RF/Analog/Serdes SoC design experience.
Knowledge and experience with analog circuits/mixed‑signal circuits such as bandgap, LDO, filters.
Knowledge and experience with Serdes IP circuits: CTLE, DFE, FFE, clock distributions, PI, IQ generation.
Knowledge of Serdes architecture and high‑speed interconnect standards (USB, PCIe, UCIe).
Knowledge and experience with ESD, PLL, clock generation, ADC, DAC is a big plus.
Well‑versed in EDA tools (Cadence, Spectre, Totem, EMX).
Comfortable with scripting languages (Python, Matlab).
Inclusive, collaborative, innovative, and a lifelong learner.
What we offer Base Pay Range: $180,950–$289,050 USD. The role includes a comprehensive benefits package: medical, dental, vision, 401(k), paid time off, family support, wellness resources, and flexibility.
Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. We provide comprehensive accommodations for candidates with disabilities, long‑term conditions, neurodivergent individuals, or those requiring pregnancy‑related support throughout our recruiting processes.
Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies with a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.
Applicant AI Use Policy We prohibit the use of generative AI tools to misrepresent a candidate’s true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research. All submitted content and interview responses must reflect the candidate’s genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process.
Applicant Privacy Policy https://semiconductor.samsung.com/about-us/careers/us/privacy/
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Location Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy.
What you’ll do
Design low‑power and low‑voltage analog and custom digital circuit components using advanced CMOS process technologies.
Translate component design specifications to schematics and build simulation test‑benches to evaluate circuit performance, functionality, power consumption, and reliability.
Supervise layout designers to generate LVS/DRC clean layout and optimize layout to improve power consumption and performance of circuits.
Validate functionality and performance in silicon.
What you bring
Bachelor’s with 15+ years, Master’s with 13+ years or PhDs with 10+ years of experience.
Minimum 2+ years of RF/Analog/Serdes SoC design experience.
Knowledge and experience with analog circuits/mixed‑signal circuits such as bandgap, LDO, filters.
Knowledge and experience with Serdes IP circuits: CTLE, DFE, FFE, clock distributions, PI, IQ generation.
Knowledge of Serdes architecture and high‑speed interconnect standards (USB, PCIe, UCIe).
Knowledge and experience with ESD, PLL, clock generation, ADC, DAC is a big plus.
Well‑versed in EDA tools (Cadence, Spectre, Totem, EMX).
Comfortable with scripting languages (Python, Matlab).
Inclusive, collaborative, innovative, and a lifelong learner.
What we offer Base Pay Range: $180,950–$289,050 USD. The role includes a comprehensive benefits package: medical, dental, vision, 401(k), paid time off, family support, wellness resources, and flexibility.
Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. We provide comprehensive accommodations for candidates with disabilities, long‑term conditions, neurodivergent individuals, or those requiring pregnancy‑related support throughout our recruiting processes.
Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies with a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.
Applicant AI Use Policy We prohibit the use of generative AI tools to misrepresent a candidate’s true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research. All submitted content and interview responses must reflect the candidate’s genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process.
Applicant Privacy Policy https://semiconductor.samsung.com/about-us/careers/us/privacy/
#J-18808-Ljbffr