NVIDIA
Senior Mixed Signal Design Engineer
Join NVIDIA as a Senior Mixed Signal Design Engineer. We are looking for a Senior Mixed‑Signal/Analog/IO Circuit Design Engineer to join a rapidly growing team pushing the frontiers of high‑speed DRAM SerDes solutions. NVIDIA is a learning machine constantly evolving by adapting to new opportunities that matter to the world.
What You’ll Be Doing
Design mixed‑signal/analog circuits for high‑speed memory I/O interfaces.
Address challenges of circuit designs in the latest CMOS FinFET processes.
Take designs through productization and be actively involved in all stages of development.
Collaborate with multi‑functional teams to optimise designs.
Qualifications
8+ years of high‑speed DRAM (LPDDR5/6, DDR5/6, GDDR6/7, HBM3/4) or other SerDes interface‑related design experience.
MS/PhD in Electrical Engineering or equivalent experience.
In‑depth knowledge of deep sub‑micron CMOS FinFET process and related circuit design issues.
Strong background with Cadence custom design tools, circuit simulators such as Hspice, XA, FineSim, Spectre.
Knowledge of Verilog, Nanotime, Matlab or similar tools is a plus.
Strong interpersonal skills and teamwork.
Compensation & Benefits Your base salary will be determined based on location, experience, and market. The base salary range is $168,000 – $264,500 for Level 4 and $196,000 – $310,500 for Level 5. You will also be eligible for equity and additional benefits.
Application Deadline Applications accepted until October 12, 2025.
EEO Statement NVIDIA is committed to fostering a diverse work environment and is an equal‑opportunity employer. NVIDIA does not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
Job ID: JR2005166
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What You’ll Be Doing
Design mixed‑signal/analog circuits for high‑speed memory I/O interfaces.
Address challenges of circuit designs in the latest CMOS FinFET processes.
Take designs through productization and be actively involved in all stages of development.
Collaborate with multi‑functional teams to optimise designs.
Qualifications
8+ years of high‑speed DRAM (LPDDR5/6, DDR5/6, GDDR6/7, HBM3/4) or other SerDes interface‑related design experience.
MS/PhD in Electrical Engineering or equivalent experience.
In‑depth knowledge of deep sub‑micron CMOS FinFET process and related circuit design issues.
Strong background with Cadence custom design tools, circuit simulators such as Hspice, XA, FineSim, Spectre.
Knowledge of Verilog, Nanotime, Matlab or similar tools is a plus.
Strong interpersonal skills and teamwork.
Compensation & Benefits Your base salary will be determined based on location, experience, and market. The base salary range is $168,000 – $264,500 for Level 4 and $196,000 – $310,500 for Level 5. You will also be eligible for equity and additional benefits.
Application Deadline Applications accepted until October 12, 2025.
EEO Statement NVIDIA is committed to fostering a diverse work environment and is an equal‑opportunity employer. NVIDIA does not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
Job ID: JR2005166
#J-18808-Ljbffr