Senior ASIC Front‑End RTL Engineer – Pixel IP (SoC)

A leading technology company in Cupertino seeks an experienced ASIC Design Engineer for its Pixel IP design team. The role entails designing and manufacturing high-performance processing engines responsible for handling digital images and videos. Candidates should possess a Bachelors Degree in EE/CE, extensive experience in digital hardware design, and familiarity with low-power techniques. Competitive compensation includes base salary ranging from $181,100 to $318,400, along with benefits like medical coverage and stock options. #J-18808-Ljbffr