Senior DFT & STA Engineer for Cloud AI ASICs

A leading technology company in Sunnyvale seeks a Senior DFT Static Timing Analysis Engineer to shape the future of AI/ML hardware acceleration. Responsibilities include timing constraint creation, validation, and achieving timing closure for complex ASICs. Candidates should have experience in static timing analysis and engineering change order processes. Preferred qualifications include advanced degrees and extensive experience in DFT methodologies. Join a team that's redefining what's possible in AI and infrastructure. #J-18808-Ljbffr