RTL Synthesis CAD Engineer — GenAI-Driven Optimization

A leading tech company in San Diego seeks an engineer to join their dynamic team focused on evolving RTL and Synthesis solutions. The role demands knowledge in SystemVerilog and a solid background in Synthesis and Place & Route for Snapdragon chips. Candidates should have a relevant degree and 1-4 years of CAD experience. This position offers a competitive salary range and benefits. Opportunities for innovation and collaboration with talented teams make this a unique role in semiconductor design. #J-18808-Ljbffr