IP Verification Engineer – FPGA/ASIC Front‑End Expert

A leading semiconductor company in San Jose, CA is seeking a Verification Engineer to collaborate on ASIC and FPGA projects. This role focuses on developing UVM-based test environments and ensures high design quality through rigorous testing. Ideal candidates have strong skills in Verilog, System Verilog, and a background in IP level verification. Join a culture of innovation and contribute to cutting-edge technology developments. #J-18808-Ljbffr