Senior ASIC Digital Design Lead for DDR IP

A leading semiconductor company is seeking an ASIC Digital Design, Sr Manager to lead design teams in developing innovative DDR PHY IP solutions. The role requires extensive experience in Verilog and SystemVerilog, strong management skills, and the ability to navigate complex design processes. You will work closely with cross-functional teams to ensure project success and mentor engineers while fostering a culture of innovation. This position offers a dynamic environment where strategic thinking and leadership are essential. #J-18808-Ljbffr