Senior Analog Mask Design Engineer – CMOS Layout

A leading semiconductor company in Portland is seeking a mid-level Mask Design Engineer. In this role, you will create integrated circuit layouts, collaborating with design engineers and ensuring high-quality designs using Cadence tools. Ideal candidates should possess strong problem-solving and communication skills, as well as substantial experience in analog layout design. This position offers a dynamic team environment focused on innovation and excellence. #J-18808-Ljbffr