Validation Engineer - DDR5/LPDDR5 & FPGA Expert

A global technology solutions provider is looking for a Mid-Senior level engineer in San Jose, California. This role involves developing test plans and validating Memory interfaces such as DDR5/LPDDR5. Candidates should have significant experience in engineering, particularly in FPGA validation and lab environments. Knowledge of scripting languages is preferred. This is a contract position with a pay range of $70.00/hr - $85.00/hr. #J-18808-Ljbffr