RISC‑V AI‑CPU Verification Lead – Hybrid

A leading tech company is looking for a Design Verification Lead to develop the verification strategy for RISC-V CPU architecture. The role requires 8+ years of experience in CPU verification, expertise in SystemVerilog and UVM, and strong Python scripting skills. The ideal candidate will mentor engineers and ensure designs meet functional and performance requirements. This hybrid position is based in Santa Clara, CA, with competitive compensation ranging from $100k to $500k depending on experience and skills. #J-18808-Ljbffr