Staff STA Engineer: DFT & Timing Lead for AI SoCs

A leading AI technology company is looking for a Staff Design for Test STA Engineer. You will ensure the testability and performance of next-generation AI processors. The ideal candidate has deep knowledge of DFT concepts and experience in Static Timing Analysis for complex SoCs. This hybrid role is based in Santa Clara, CA. Applicants will be assessed for various experience levels and compensation ranges from $100k to $500k based on skills and education. #J-18808-Ljbffr