Netpace Inc
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This range is provided by Netpace Inc. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range $210,000.00/yr - $270,000.00/yr
Direct message the job poster from Netpace Inc
2X “Chairman’s Club” Winner// 4X “Account Breaker”// “Rising Star” award Winner // Strategy-driven Leader for upscaling Teams dedicated to finding… About our Client:
Our Customer is an esteemed, fast-growing, Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today’s AI model performance is often gated by infrastructure bottlenecks. Our Client introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Their solution and value proposition have been widely validated with several hyperscalers.
The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED display company and developer of the first augmented reality contact lens).
Position Overview
We are seeking a highly experienced and motivated Clock Designer – Design Lead to drive the definition, architecture, and implementation of high-speed clock distribution networks for complex, large-scale SoC designs. This role is critical in ensuring high-performance, low-skew clocking solutions across multi-core, multi-module systems at advanced process nodes (7nm and below).
Responsibilities
Lead the architecture definition and implementation of high-speed clock distribution networks in large-scale ICs.
Define and manage clock architecture specifications, timing budgets, and design methodologies for SoC designs.
Perform clock distribution design modeling, analysis, and implementation to meet aggressive timing and power targets.
Drive post-silicon clock distribution characterization and debug, identifying performance bottlenecks and optimizing solutions.
Develop cross-clock domain data transfer logic and ensure reliable synchronization across timing domains.
Design and implement de-skew mechanisms and cross-clock domain communication protocols.
Collaborate with physical design teams for optimal clock tree synthesis, floorplanning, and integration into SoC flows.
Own the clocking solution from concept to tape-out, ensuring first-pass silicon success across multiple technology nodes.
Build and evolve clocking design methodologies, ensuring robust, reusable, and scalable design practices.
Support synthesis, STA, and integration teams with design constraints (SDC/CDC) and cross-domain timing closure.
Participate in system-level architecture reviews and cross-functional discussions to drive overall design quality and performance.
Qualifications:
Bachelor’s or Master’s degree in Electrical Engineering or a related field.
15+ years of industry experience in custom circuit design and clock distribution networks for high-speed SoCs.
Demonstrated leadership in delivering complex clock architectures and clock distribution implementations across several tapeouts.
Expertise in clock timing analysis, budgeting, and hands‑on experience with clock de‑skew and domain crossing techniques.
Proficiency in physical implementation tools such as Cadence Innovus/Genus or Synopsys Fusion Compiler.
Strong scripting skills in Unix, Perl, Python, or TCL for automation and analysis.
Excellent understanding of synthesis design constraints (SDC, CDC) and their impact on timing and verification.
Strong communication and problem‑solving skills, with the ability to lead cross‑functional teams.
Proven ability to deliver results under aggressive schedules, with a high level of accountability and motivation.
Preferred Qualifications
Prior experience with EMIB architectures and interconnect bridge designs.
Familiarity with Verilog and SystemVerilog.
Multiple tapeouts in deep submicron nodes (7nm or below).
Why Join Us?
With our Client, you’ll have the opportunity to shape the future of AI infrastructure, working with a world‑class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.
Seniority level Mid‑Senior level
Employment type Full‑time
Job function Semiconductor Manufacturing, Information Technology & Services, and Manufacturing
Referrals increase your chances of interviewing at Netpace Inc by 2x
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Get AI-powered advice on this job and more exclusive features.
This range is provided by Netpace Inc. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range $210,000.00/yr - $270,000.00/yr
Direct message the job poster from Netpace Inc
2X “Chairman’s Club” Winner// 4X “Account Breaker”// “Rising Star” award Winner // Strategy-driven Leader for upscaling Teams dedicated to finding… About our Client:
Our Customer is an esteemed, fast-growing, Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today’s AI model performance is often gated by infrastructure bottlenecks. Our Client introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Their solution and value proposition have been widely validated with several hyperscalers.
The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED display company and developer of the first augmented reality contact lens).
Position Overview
We are seeking a highly experienced and motivated Clock Designer – Design Lead to drive the definition, architecture, and implementation of high-speed clock distribution networks for complex, large-scale SoC designs. This role is critical in ensuring high-performance, low-skew clocking solutions across multi-core, multi-module systems at advanced process nodes (7nm and below).
Responsibilities
Lead the architecture definition and implementation of high-speed clock distribution networks in large-scale ICs.
Define and manage clock architecture specifications, timing budgets, and design methodologies for SoC designs.
Perform clock distribution design modeling, analysis, and implementation to meet aggressive timing and power targets.
Drive post-silicon clock distribution characterization and debug, identifying performance bottlenecks and optimizing solutions.
Develop cross-clock domain data transfer logic and ensure reliable synchronization across timing domains.
Design and implement de-skew mechanisms and cross-clock domain communication protocols.
Collaborate with physical design teams for optimal clock tree synthesis, floorplanning, and integration into SoC flows.
Own the clocking solution from concept to tape-out, ensuring first-pass silicon success across multiple technology nodes.
Build and evolve clocking design methodologies, ensuring robust, reusable, and scalable design practices.
Support synthesis, STA, and integration teams with design constraints (SDC/CDC) and cross-domain timing closure.
Participate in system-level architecture reviews and cross-functional discussions to drive overall design quality and performance.
Qualifications:
Bachelor’s or Master’s degree in Electrical Engineering or a related field.
15+ years of industry experience in custom circuit design and clock distribution networks for high-speed SoCs.
Demonstrated leadership in delivering complex clock architectures and clock distribution implementations across several tapeouts.
Expertise in clock timing analysis, budgeting, and hands‑on experience with clock de‑skew and domain crossing techniques.
Proficiency in physical implementation tools such as Cadence Innovus/Genus or Synopsys Fusion Compiler.
Strong scripting skills in Unix, Perl, Python, or TCL for automation and analysis.
Excellent understanding of synthesis design constraints (SDC, CDC) and their impact on timing and verification.
Strong communication and problem‑solving skills, with the ability to lead cross‑functional teams.
Proven ability to deliver results under aggressive schedules, with a high level of accountability and motivation.
Preferred Qualifications
Prior experience with EMIB architectures and interconnect bridge designs.
Familiarity with Verilog and SystemVerilog.
Multiple tapeouts in deep submicron nodes (7nm or below).
Why Join Us?
With our Client, you’ll have the opportunity to shape the future of AI infrastructure, working with a world‑class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.
Seniority level Mid‑Senior level
Employment type Full‑time
Job function Semiconductor Manufacturing, Information Technology & Services, and Manufacturing
Referrals increase your chances of interviewing at Netpace Inc by 2x
#J-18808-Ljbffr